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參數(shù)資料
| 型號： | AD9200JRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT CMOS 20MSPS 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
AD9200
–8–
REV. E
Table I. Mode Selection
Input
MODE
REFSENSE
Modes
Connect
Span
Pin
REF
REFTS
REFBS
Figure
TOP/BOTTOM
AIN
1 V
AVDD
Short REFSENSE, REFTS and VREF Together
AGND
18
AIN
2 V
AVDD
AGND
Short REFTS and VREF Together
AGND
19
CENTER SPAN
AIN
1 V
AVDD/2
Short VREF and REFSENSE Together
AVDD/2
20
AIN
2 V
AVDD/2
AGND
No Connect
AVDD/2
Differential
AIN Is Input 1
1 V
AVDD/2
Short VREF and REFSENSE Together
AVDD/2
29
REFTS and
REFBS Are
Shorted Together
for Input 2
2 V
AVDD/2
AGND
No Connect
AVDD/2
External Ref
AIN
2 V max AVDD
AVDD
No Connect
Span = REFTS
21, 22
– REFBS (2 V max)
AGND
Short to
23
VREFTF
VREFBF
AD876
AIN
2 V
Float or
AVDD
No Connect
Short to
30
AVSS
VREFTF
VREFBF
0
–9
1.0E+6
1.0E+9
10.0E+6
AMPLITUDE
–
dB
100.0E+6
–3
–6
FREQUENCY – Hz
–12
–15
–18
–21
–24
–27
Figure 13. Full Power Bandwidth
25
20
–25
0
3.0
1.0
2.0
15
10
–5
–10
–15
INPUT VOLTAGE – V
5
0
–20
2.5
0.5
1.5
I B
–
A
REFBS = 0.5V
REFTS = 2.5V
CLOCK = 20MHz
Figure 14. Input Bias Current vs. Input Voltage
APPLYING THE AD9200
THEORY OF OPERATION
The AD9200 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9200 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9200 requires a small fraction of the
1023 comparators used in a traditional flash type A/D. A
sample-and-hold function within each of the stages permits the
first stage to operate on a new input sample while the second,
third and fourth stages operate on the three preceding samples.
OPERATIONAL MODES
The AD9200 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876 A/D.
To realize this flexibility, internal switches on the AD9200 are
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
of the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli-
cation will determine which mode is appropriate: the descrip-
tions in the following sections, as well as the Table I should
assist in picking the desired mode.
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