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參數(shù)資料
| 型號： | AD9042ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 41MSPS 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 41M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 735mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
AD9042
Rev. B | Page 14 of 24
If no TTL source is available, a clean sine wave can be substituted.
In the case of the sine source, the matching network is shown in
Figure 29. Because the matching transformer specified is a 1:1
impedance ratio, R, the load resistor should be selected to
match the source impedance. The input impedance of the
AD9042 is negligible in most cases.
ENCODE
AD9042
R
T1-1T
SINE
SOURCE
ENCODE
0
55
4-
0
35
Figure 29. Sine Source Differential Encode
If a low jitter ECL clock is available, another option is to ac-
couple a differential ECL signal to the encode input pins as
shown in Figure 30. The capacitors shown here should be chip
capacitors but do not need to be of the low inductance variety.
ENCODE
AD9042
ECL
GATE
0.1F
510
510
–VS
ENCODE
00
55
4-
0
36
Figure 30. Differential ECL for Encode
As a final alternative, the ECL gate can be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
ENCODE
AD9042
AD96687 (1/2)
0.1F
510
510
50
–VS
ENCODE
+
–
00
55
4-
0
37
Figure 31. ECL Comparator for Encode
Care should be taken not to overdrive the encode input pins
when ac-coupled. Although the input circuitry is electrically
protected from overvoltage or undervoltage conditions,
improper circuit operations may result from overdriving the
encode input pins.
DRIVING THE ANALOG INPUT
Because the AD9042 operates from a single 5 V supply, the
analog input range is offset from ground by 2.4 V. The analog input,
AIN, is an operational amplifier configured in an inverting mode
Because the operational amplifier forces its inputs to the same
voltage, the inverting input is also at 2.4 V. Therefore, the analog
input has a Thevenin equivalent of 250 Ω in series with a 2.4 V
source. It is strongly recommended that the internal voltage
reference of the AD9042 be used for the amplifier offset; this
reference is designed to track internal circuit shifts over
temperature.
AD9042
2.4V
REFERENCE
AIN
0.1F
VOFFSET
TIED TO
VREF
THROUGH
50
250
250
50
+
–
00
55
4-
0
38
Figure 32. Analog Input Offset by 2.4 V Reference
Although the AD9042 can be used in many applications, it was
specifically designed for communications systems that must
digitize wide signal bandwidths. As such, the analog input was
designed to be ac-coupled. Because most communications
products do not downconvert to dc, this should not pose a
problem. One example of a typical analog input circuit is shown
in Figure 33. In this application, the analog input is coupled
with a high quality chip capacitor, the value of which can be
chosen to provide a low frequency cutoff that is consistent with
the signal being sampled; in most cases, a 0.1 μF chip capacitor
works well.
0.1F
AIN
AD9042
VOFFSET
VREF
ANALOG
SIGNAL
SOURCE
RT
50
00
55
4-
0
39
Figure 33. AC-Coupled Analog Input Signal
Another option for ac coupling is a transformer. The impedance
ratio and frequency characteristics of the transformer are
determined by examining the characteristics of the input signal
source (transformer primary connection), and the AD9042
input characteristics (transformer secondary connection).
Given the transformer turns ratio, RT should be chosen to
satisfy the termination requirements of the source. A blocking
capacitor is required to prevent AD9042 dc bias currents from
flowing through the transformer.
0.1F
AIN
AD9042
VOFFSET
VREF
ANALOG
SIGNAL
SOURCE
RT
50
XFMR
LO
BPF
00
55
4-
0
40
Figure 34. Transformer-Coupled Analog Input Signal
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