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參數(shù)資料
| 型號： | AD8600APZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC MULT 16CH 8BIT 44PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時(shí)間： | 1µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 16 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 175mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 16 電壓，單極；16 電壓，雙極 |
| 采樣率（每秒）： | 1M |
REV. 0
–14–
AD8600
The functionality of this circuit is shown in the scope photo in
Figure 24 The top trace is the control ramp, which goes from
0 V to 1.25 V. The bottom trace is the output of the AD600.
The input is actually a 12 mV p-p, 10 kHz sine wave. Thus, the
bottom trace shows the envelop of this waveform to illustrate
the increase in gain as time progresses. This ramp was gener-
ated under control of the 68HC11 using the “ramp” subroutine
as mentioned above. The slope of the ramp can easily be
lengthened by adding some delay in the loop, or the slope can
be increased by stepping by 2 or more LSBs instead of the cur-
rent 1 LSB changes.
GAIN
CONTROL
1V/DIV
AD600
OUTPUT
0.2V/DIV
200s/DIV
Figure 24. Time Dependent Gain of the AD600
Glitch Impulse
A specification of interest in many DAC applications is the
glitch impulse. This is the amount of energy contained in any
overshoot when a DAC changes at its major carry transition, in
other words, when the DAC switches from code 01111111 to
code 10000000. This point is the most demanding because all
of the R-2R ladder switches are changing state. The AD8600’s
glitch impulse is shown in Figure 25. Calculating the value of
the glitch is accomplished by calculating the area of the pulse,
which for the AD8600 is: Glitch Impulse = (1/2)
× (100 mV) ×
(200 ns) = 10 nV sec.
200ns/DIV
VOUT
50mV/DIV
Figure 25. Glitch Impulse
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