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參數(shù)資料
型號(hào): AD8600APZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 11/16頁
文件大小: 0K
描述: IC DAC MULT 16CH 8BIT 44PLCC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 500
設(shè)置時(shí)間: 1µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 16
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 175mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 16 電壓,單極;16 電壓,雙極
采樣率(每秒): 1M
REV. 0
–4–
AD8600
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
INTERFACE TIMING
1, 2
Clock (EN) Frequency
fCLK
Data Loading
12.5
MHz
Clock (EN) High Pulse Width
tCH
40
ns
Clock (EN) LowPulse Width
tCL
40
ns
Data Setup Time
tDS
40
ns
Data Hold Time
tDH
10
ns
Address Setup Time
tAS
0ns
Address Hold Time
tAH
0ns
Valid Address to Data Valid
tAD
160
ns
Load Enable Setup Time
tLS
0ns
Load Enable Hold Time
tLH
0ns
Read/Write to Clock (EN)tRWC
30
ns
Read/Write to DataBus Hi-Z
tRWZ
120
ns
Read/Write to DataBus Active
tRWD
120
ns
Clock (EN) to Read/Write
tTWH
0ns
Clock (EN) to Chip Select
tTCH
0ns
Chip Select to Clock (EN)tCSC
30
ns
Chip Select to Data Valid
tCSD
120
ns
Chip Select to DataBus Hi-Z
tCSZ
150
ns
Reset Pulse Width
tRS
25
ns
NOTES
1Guaranteed by design not subject to production test.
2All logic input signals have maximum rise and fall times of 2 ns.
Specifications subject to change without notice.
Figure 3. Readback Timing
Figure 2. Write Timing
(@ VDD1 = VDD2 = VCC = +5 V
± 5%, V
EE = –5 V, VREF = +3.500 V, – 40
°C ≤ T
A
≤ +85°C,
unless otherwise noted)
tRWZ
tDH
tTWH
HIGH-Z
tAS
tAH
tCH
tCL
tTCH
R/W
DATA
ADDR
EN
CS
tCSC
tRWC
tDS
Figure 4. Write to DAC Register & Voltage Output Settling
Timing (CS= High, Prevents Input Register Changes)
tLS
tLH
tS1
tRS
OUT
tS1
EN
RS
LD
tRWD
HIGH -Z
tAD
tCSZ
tCSD
R/W
DATA
ADDR
EN
CS
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