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參數(shù)資料
| 型號： | AD8432-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD8432 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 每 IC 通道數(shù)： | 2 - 雙 |
| 放大器類型： | 電壓反饋 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 295 V/µs |
| -3db帶寬： | 200MHz |
| 電流 - 輸出 / 通道： | 77mA |
| 工作溫度： | -40°C ~ 85°C |
| 電流供應(yīng)（主 IC）： | 24mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 板類型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD8432 |
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AD8432
Data Sheet
Rev. C | Page 18 of 32
THEORY OF OPERATION
LOW NOISE AMPLIFIER (LNA)
The AD8432 is a dual-channel, ultralow noise amplifier with
integrated pin-strappable, gain-setting resistors. The resistors
can be externally connected to achieve differential gains of
12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (×4, ×8, ×12, and
×16, respectively). A simplified schematic of an LNA is shown
The LNA is driven with a single-ended input and measured
differentially at the output. The inverting input INL must be
ac-coupled to ground through a capacitor for proper operation.
The LNA cannot be driven differentially due to the asymmetry
of the internal gain setting resistors. The gain from the inverting
input INL to the single-ended output (OPH or OPL) does not
match the gain from the noninverting input INH to the single-
ended output.
The AD8432 inputs have a dc bias voltage of 3.25 V, which is
generated internally. The inputs must be ac-coupled through a
series capacitor to maintain the dc bias level of the inputs. Likewise,
the AD8432 outputs have a dc bias voltage of 2.5 V. An ac coupling
capacitor in series with each single-ended output is recommended
to prevent improper loading of the outputs. The AD8432 inputs
have a dc bias voltage of 3.25 V, which is generated internally.
The inputs must be ac-coupled through a series capacitor to
maintain the dc bias level of the inputs (see CINL and CINH
The AD8432 supports a differential output voltage of 4.8 V p-p
for the common-mode output voltage of 2.5 V. Therefore, for a
differential gain of G = 12.04 dB, the maximum input voltage
allowed is 1.2 V p-p.
Clamping the inputs ensures quick recovery from large input
voltages. The input back-to-back diodes, which are integrated
inside the die (IND1 and IND2), should be used for the lowest gain
configuration (12.04 dB) to protect the input from overdriving.
They should be connected after the source resistance or before
the INH coupling capacitor.
The use of a fully differential topology and negative feedback
minimizes distortion. A differential signal enables smaller swings at
each output, which results in reduction of third-order distortion.
The AD8432 is a voltage feedback amplifier. Due to gain band-
width product (GBW), a decrease in bandwidth should be
expected as the gain increases. Table 5 displays the values of the
3 dB bandwidth for each gain with unterminated input
impedance.
GAIN SETTING TECHNIQUE
Pin strapping is used to set the gain of the amplifier. Gain setting
resistors are integrated in the LNA and are accessible externally
through the GOH, GMH, GML, and GOL pins. By externally
shorting these pins, and thereby shorting or connecting the
internal resistors, the AD8432 can be configured for four different
gains. Table 5 shows which pins must be connected to achieve
the desired gain.
RG2
12
RG3
24
RG4
48
RG7
48
RG6
24
RG5
24
RG1
12
I
CINH
INH
OPH
VPS
OPL
INL
RFB
CFB
Q2
Q1
GMH
GOH
GML
GOL
CINL
GND
RSH
RS
CSH
VS
08341-
065
Figure 65. Simplified Schematic of a Single LNA Channel, Including External Shunt and Feedback Components
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