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參數(shù)資料
| 型號(hào)： | AD8396ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DRVR ADSL/ADSL2 16LFCSP |
| 產(chǎn)品變化通告： | AD8396 Package Change 11/Sept/2009 AD8396 Discontinuation 17/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 線路驅(qū)動(dòng)器，發(fā)射器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/0 |
| 電源電壓： | 6 V ~ 24 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-WQ（4x4） |
| 包裝： | 帶卷 (TR) |
AD8396
Rev. C | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage, VCC VEE
26.4 V
Power Dissipation
See Figure 3
Figure 3 shows the maximum power dissipation in the package
vs. the ambient temperature for the 16-lead LFCSP on a JEDEC
standard 4-layer board. θJA values are approximations.
3.5
0
–25
85
AMBIENT TEMPERATURE (°C)
M
AX
IM
UM
P
O
W
E
R
DI
S
IP
AT
IO
N
(
W
)
Storage Temperature Range
65°C to +150°C
Operating Temperature Range
40°C to +85°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified in still air with exposed pad soldered to 4-layer
JEDEC test board. θJC is specified at the exposed pad.
Table 3.
Package Type
θJA
θJC
Unit
16-Lead LFCSP
56
9.1
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8396 is limited
by its junction temperature on the die.
The maximum safe junction temperature of plastic encapsulated
devices, as determined by the glass transition temperature of the
plastic, is 150°C. Exceeding this limit can temporarily cause a shift
in the parametric performance due to a change in the stresses
exerted on the die by the package. Exceeding this limit for an
extended period can result in device failure.
–15
–5
5
1525
354555
6575
07
02
2-
0
03
TJ = 150°C
3.0
2.5
2.0
1.5
1.0
0.5
Figure 3. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming that the load RL is referenced
to midsupply, the total drive power is VS/2 × IOUT, part of which
is dissipated in the package and part in the load (VOUT × IOUT).
RMS output voltages should be considered. If RL is referenced to
VEE, as in single-supply operation, the total power is VS × IOUT.
In single supply with RL to VEE, worst case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more copper in direct contact with the package leads
from PCB traces, through-holes, ground, and power planes
reduces θJA.
ESD CAUTION
OBSOLETE
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