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| 型號： | AD8396ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DRVR ADSL/ADSL2 16LFCSP |
| 產(chǎn)品變化通告： | AD8396 Package Change 11/Sept/2009 AD8396 Discontinuation 17/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 線路驅(qū)動器，發(fā)射器 |
| 驅(qū)動器/接收器數(shù)： | 2/0 |
| 電源電壓： | 6 V ~ 24 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-WQ（4x4） |
| 包裝： | 帶卷 (TR) |
AD8396
Rev. C | Page 9 of 12
APPLICATIONS INFORMATION
SUPPLIES, GROUNDING, AND LAYOUT
The AD8396 can be powered from either single or dual supplies,
with the total supply voltage ranging from 12 V to 24 V. For
optimum performance, use well-regulated low ripple supplies.
As with all high speed amplifiers, pay close attention to supply
decoupling, grounding, and overall board layout. Provide low
frequency supply decoupling with 10 μF tantalum capacitors
from each supply to ground. In addition, decouple all supply
pins with 0.1 μF quality ceramic chip capacitors placed as close
as possible to the driver. Use an internal low impedance ground
plane to provide a common ground point for all driver and
decoupling capacitor ground requirements. Whenever possible,
use separate ground planes for analog and digital circuitry.
Follow high speed layout techniques to minimize parasitic
capacitance.
Keep input and output traces as short as possible and as far
apart from each other as practical to minimize crosstalk. Keep
all differential signal traces as symmetrical as possible.
POWER MANAGEMENT
A digitally programmable logic pin switches each port of the
AD8396 between active bias and shutdown states. The PD_A
pin controls Port A and the PD_B pin controls Port B. These
pins can be controlled directly with either 3.3 V or 5 V CMOS
logic with the DGND pins as a reference. If left unconnected,
the PD pins float high, placing the amplifier in the shutdown
state. See the Specifications section for the quiescent current for
each of the available bias states.
TYPICAL ADSL/ADSL2+ APPLICATION
In a typical ADSL/ADSL2+ application, a differential line driver
takes the signal from the analog front end (AFE) and drives it
onto the twisted pair telephone line. Referring to the typical
circuit representation in Figure 14, the differential input appears
at VIN+ and VIN from the AFE, while the differential output is
transformer coupled to the telephone line at TIP and RING.
The common-mode operating point, generally midway between
the supplies, is set internally and
is available at VCOM.
VCC
4k
VEE
+
–
VCOM
0.1F
+
VIN+
VIN–
1:N
TIP
RING
ROUT
Rm
07
02
2-
01
4
Figure 14. Typical ADSL/ADSL2+ Application Circuit
MULTITONE POWER RATIO (MTPR)
The DMT signal used in ADSL/ADSL2+ systems carries data in
discrete tones or bins, which appear in the frequency domain in
evenly spaced 4.3125 kHz intervals. In applications using this type
of waveform, MTPR is a commonly used measure of linearity.
Generally, designers are concerned with two types of MTPR:
in-band and out-of-band. In-band MTPR is defined as the
measured difference from the peak of one tone that is loaded
with data to the peak of an adjacent tone that is intentionally
left empty. Out-of-band MTPR is more loosely defined as the
spurious emissions that occur in the receive band located between
25.875 kHz and the first downstream tone at 138 kHz. Figure 15
and Figure 16 show the AD8396 in-band MTPR for a 5.5 crest
factor waveform for empty bins in the ADSL and extended
ADSL2+ bandwidths.
0
–100
642.131
651.619
FREQUENCY (kHz)
M
A
G
N
IT
UDE
(
d
Bm)
–20
–10
–30
–50
–70
–90
–40
–60
–80
644.503
646.875
649.247
–73dBc
07
02
2-
0
15
Figure 15. In-Band MTPR at 646.875 kHz
1.9618
1.9712
FREQUENCY (MHz)
M
A
G
N
IT
UDE
(
d
Bm)
1.9641
1.9665
1.9689
–68dBc
07
02
2-
0
16
0
–100
–20
–10
–30
–50
–70
–90
–40
–60
–80
Figure 16. In-Band MTPR at 1.9665 MHz
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