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| 型號： | AD8368ACPZ-WP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP VGA 24LFCSP |
| 設(shè)計資源： | Extending the Dynamic Range of ADL5513 Logarithmic Detector Using AD8368 (CN0072) |
| 標(biāo)準(zhǔn)包裝： | 64 |
| 系列： | X-AMP® |
| 放大器類型： | 可變增益 |
| 電路數(shù)： | 1 |
| -3db帶寬： | 800MHz |
| 電流 - 電源： | 60mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 托盤 - 晶粒 |
AD8368
Rev. B | Page 17 of 20
EVALUATION BOARD
The standard evaluation board schematic and layout artwork is
is fabricated on a multilayer FR-4 board, with 50 Ω-controlled
impedance transmission lines for the RF input and output traces.
The board is powered by a single supply in the 4.5 V to 5.5 V
range. The power supply is decoupled by 0.1 μF and 1 nF capacitors
at each power supply pin. Additional decoupling, in the form
of a series resistor or inductor at the supply pins, can also be added.
Table 6 details the various configuration options of the
evaluation board.
05
90
7-
0
43
VPOS
VPOS1 VPOS2 VPOS3
IC
O
M
GA
IN
ENBL
VPSI
MODE
ICOM
INPT
OCOM
OUTP
VPSO
VPSI
IC
O
M
DE
T
O
IC
O
M
HP
F
L
DE
CL
DE
C
L
DE
CL
DE
T
I
V
PSI
OC
OM
AD8368
C20
1nF
C2
5.6pF
C11
1nF
C14
0.1F
R11
0
VPOS2
C12
1nF
C15
0.1F
R12
0
VPOS3
COUT
10nF
OUTPUT
R31
OPEN
R32
OPEN
R30
OPEN
DET_IN
C1
OPEN
GAIN
C23
10nF
C4
1nF
C6
1nF
JP4
GAIN
C13
0.1F
DET_OUT_TP
R35
OPEN
R3
215
L1
10nH
CIN
10nF
INPUT
SW1
SW2
LOW
HI
ON
OFF
C10
1nF
R1
10k
R2
10k
ENABLE
R10
0
VPOS1
Figure 40. Evaluation Board
Table 6. Evaluation Board Configuration Options
Component
Function
Default Conditions
R1, R2, R3, L1
Pull-Down Resistors for MODE and ENBL. RL network. Prevent potential instability impact
due to PCB parasitics and/or certain extreme conditions (see the Stability and Layout
Considerations section).
R1 = R2 = 10 kΩ
R3 = 215 Ω
L1 = 10 nH
R10, R11, R12,
C10, C11, C12,
C13, C14, C15
Supply Decoupling. Jumpers, power supply decoupling resistors, and filter capacitors.
R10 = R11 = R12 = 0 Ω
C10 = C11 = C12 = 1 nF
C13 = C14 = C15 = 0.1 μF
CIN
RF Input. CIN provides dc block for RF input.
CIN = 10 nF
COUT
RF Output. COUT provides dc block for RF output.
COUT = 10 nF
R31, R32
Feedback Path for AGC Operation. For a default setpoint of 63 mV rms, set R31 = 0 Ω and
remove R32. For other AGC setpoints, rms voltage = (1 + n) × 63 mV rms, where n = R31/R32.
R31 = R32 = Open
(VGA mode)
R35
Populate with 0 Ω to feed detector output RSSI voltage to DET_OUT_TP.
R35 = Open
C23
Sets the corner frequency of the output offset control loop high-pass filter.
C23 = 10 nF
C1, R30
Used for driving the detector externally. Set R30 to 50 Ω for matching. Set C1 to be a large
ac coupling capacitor.
C1 = Open
R30 = Open
C6
DETO Capacitor. Needs to be made larger for lower data rates (see the AGC Operation section).
C6 = 1 nF
C20, C2, C4
DECL Capacitor. Needs to be adjusted based on RF frequency in AGC operation (see the
AGC Operation section).
C20 = C4 = 1 nF
C2 = 5.6 pF
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