參數(shù)資料
型號(hào)： AD8368ACPZ-WP
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 0K
描述： IC AMP VGA 24LFCSP
設(shè)計(jì)資源： Extending the Dynamic Range of ADL5513 Logarithmic Detector Using AD8368 (CN0072)
標(biāo)準(zhǔn)包裝： 64
系列： X-AMP®
放大器類型： 可變?cè)鲆?br>
電路數(shù)： 1
-3db帶寬： 800MHz
電流 - 電源： 60mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-VQ（4x4）
包裝： 托盤 - 晶粒
AD8368
Rev. B | Page 14 of 20
APPLICATIONS INFORMATION
VGA OPERATION
The AD8368 is a general-purpose VGA suitable for use in a wide
variety of applications where accurate, continuous, linear-in-dB
gain control over a broad range of frequencies is important. Its
stability over temperature and supply in comparison to other
variable gain techniques can be traced back to the X-AMP
architecture. While having an 800 MHz bandwidth, its low
frequency operation can be extended by properly selecting
CHPFL and CDECL.
The typical connections for using the AD8368 in VGA mode are
illustrated in Figure 33. The input (INPT) and output (OUTP) of
the AD8368 should be externally ac-coupled to prevent disrupting
the dc levels on the chip. Therefore, a sufficiently large coupling
capacitor should be used such that the series impedance of the
capacitor is negligible at the frequencies of interest.
05
90
7-
03
6
ICOM
GAIN
EN
B
L
VPS
I
VPS
I
MO
D
E
IC
OM
IN
P
T
OC
OM
OU
TP
V
PSO
V
PSO
V
PSI
V
PSI
ICOM
DETO
ICOM
HPFL
DECL
DETI
VPSI
OCOM
AD8368
VGAIN
0V TO 1V
VPOS
VIN
REF
X2
–
+
VPOS
VOUT
Figure 33. Typical Connections for VGA Mode for
Increasing Gain with Increasing VGAIN (MODE High)
The gain control voltage ranging from 0 V to 1 V is applied to
the GAIN pin. The MODE pin controls whether the gain of the
part is an increasing or decreasing function of the gain voltage.
When the MODE pin is pulled high, the gain increases with
increasing gain voltages. When the MODE pin is pulled low, the
gain decreases with increasing gain voltages. The ENBL pin is
used to enable or disable the part. ENBL is active high; when
ENBL is pulled low, the part is disabled and draws a fraction of
the normal supply current.
The DECL pin provides the internal midsupply dc reference
for the AD8368. It should be well decoupled to ground using a
large capacitor with low ESR. The capacitors connected to the
HPFL pin and DECL pin are used to control the low-pass
corner frequency of the output offset correction loop. The
resulting high-pass corner frequency is inversely proportional
to their values.
AGC OPERATION
The AD8368 can be configured as a standalone AGC amplifier
by using the on-board rms detector, as shown in Figure 34. The
detector output, DETO, is an error current representing the
difference of squares between the root-mean-square (rms) of
the sensed signal and an internal reference of 63 mV rms. This
error current is integrated on CDETO and connected to the GAIN
pin to form the AGC loop.
The 63 mV rms reference corresponds to 178 mV p-p for a sine
wave but the detector accuracy is maintained for more complex
signals, such as Gaussian noise, complex envelopes, and multi-
carrier signals with high peak-to-average ratios.
05
90
7-
03
7
ICOM
GAIN
E
NBL
VP
SI
VP
SI
MO
D
E
IC
OM
IN
P
T
OC
OM
OU
T
P
VPS
O
VPS
O
VPS
I
VPS
I
ICOM
DETO
ICOM
HPFL
DECL
DETI
VPSI
OCOM
AD8368
RSSI
CDETO
VPOS
VIN
REF
X2
–
+
VPOS
VOUT
R2
R1
Figure 34. AGC Mode of Operation
The AGC mode of operation requires a specific gain direction.
The gain must fall as VDETO increases to restore the needed
balance against the setpoint. Therefore, the MODE pin must be
pulled low. By connecting the signal at OUTP directly to the
detector input (DETI), the output level is driven to the 63 mV
rms reference setpoint.
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