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參數(shù)資料
| 型號： | AD8326AREZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DVR CATV PROG 28TSSOP |
| 產(chǎn)品變化通告： | AD8326 Series Discontinuation 28/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 線路驅(qū)動器，發(fā)射器 |
| 應(yīng)用： | CATV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-HTSSOP |
| 包裝： | 管件 |
REV. 0
AD8326
–6–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-
neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
2
SDATA
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first and ignored.
3
CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
4, 28
GND
Common External Ground Reference
5, 9, 10, 19,
VCC
Common Positive External Supply Voltage. A 0.1
F capacitor must decouple each pin.
20, 23, 27
6
TXEN
Transmit Enable pin. Logic 1 powers up the part.
7
SLEEP
Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A
Logic 0 powers down the part (High ZOUT State) and a Logic 1 powers up the part.
8, 12, 17
NC
No Connection to these pins.
11, 13, 16, 18,
VEE
Common Negative External Supply Voltage. A 0.1
F capacitor must decouple each pin.
22, 24
14
OUT–
Negative Output Signal
15
OUT+
Positive Output Signal
21
BYP
Internal Bypass. This pin must be externally ac-coupled (0.1
F capacitor).
25
VIN+
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a
0.1
F capacitor.
26
VIN–
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1
F capacitor.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD8326
DATEN
GND
SDATA
VCC
CLK
VIN–
GND
VIN+
VCC
VEE
TXEN
VCC
SLEEP
VEE
NC
BYP
VCC
VEE
NC
VEE
OUT–
OUT+
NC = NO CONNECT
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8326ARP | 制造商:Analog Devices 功能描述:SP AMP LINE DRVR AMP SGL 5.25V/12.6V 28PSOP-II - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:PSOP HIGH OUTPUT POWER CATV LINE DRIVER - Bulk |
| AD8326ARP-EVAL | 制造商:Analog Devices 功能描述:AD8326 PSOP EVALUATION BOARD 制造商:Analog Devices 功能描述:AD8326 PSOP EVALUATION BOARD - Bulk |
| AD8326ARP-REEL | 制造商:Analog Devices 功能描述: |
| AD8326ARPZ | 制造商:Analog Devices 功能描述:SP AMP LINE DRVR AMP SGL 5.25V/12.6V 28PSOP-II - Rail/Tube |
| AD8327 | 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V CATV Line Driver Coarse Step Output Power Control |
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