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參數(shù)資料
| 型號： | AD8322ARUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LN DVR CATV COARS-STP 28TSSOP |
| 產(chǎn)品變化通告： | AD8322ARUZ-REEL Discontinuation 28/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 線路驅(qū)動器，發(fā)射器 |
| 應(yīng)用： | 調(diào)制解調(diào)器，機頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD8322ARUZ-REELDKR |
REV. 0
AD8322
–3–
LOGIC INPUTS (TTL/CMOS Compatible Logic)
Parameter
Min
Typ
Max
Unit
Logic “1” Voltage
2.1
5.0
V
Logic “0” Voltage
0
0.8
V
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
020
nA
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
–600
–100
nA
Logic “1” Current (VINH = 5 V) PD
50
190
A
Logic “0” Current (VINL = 0 V) PD
–250
–30
A
TIMING REQUIREMENTS
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (TWH)
16.0
ns
Clock Period (TC)
32.0
ns
Setup Time SDATA vs. Clock (TDS)
5.0
ns
Setup Time
DATEN vs. Clock (T
ES)
15.0
ns
Hold Time SDATA vs. Clock (TDH)
5.0
ns
Hold Time
DATEN vs. Clock (T
EH)
3.0
ns
Input Rise and Fall Times, SDATA,
DATEN, Clock (T
R, TF)10
ns
(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
(
DATEN, CLK, SDATA, PD, V
CC = 5 V: Full Temperature Range)
TES
VALID DATA WORD G1
MSB. . . .LSB
GAIN TRANSFER (G1)
TDS
TEH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
TOFF
TGS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PD
PEDESTAL
CLK
SDATA
DATEN
TON
TC
TWH
VALID DATA WORD G2
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB
MSB-1
MSB-2
TDS
TDH
SDATA
CLK
Figure 3. SDATA Timing
Table I. Gain vs. Gain Code
Decimal
8-Bit SPI Data Word
Gain Code
MSB
LSB
Nominal Gain (dB)
1
0 0000 001
–12.64
2
0 0000 010
–6.62
4
0 0000 100
–0.60
8
0 0001 000
5.42
16
0 0010 000
11.44
32
0 0100 000
17.46
64
0 1000 000
23.48
128
1 xxxxxxx
29.50
0 = low, 1 = high, x = don’t care.
OBSOLETE
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