VS
參數(shù)資料
型號(hào)： AD8251-EVALZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD8251 PGA
標(biāo)準(zhǔn)包裝： 1
系列： iCMOS®
每 IC 通道數(shù)： 1 - 單
放大器類型： 儀表
輸出類型： 單端
轉(zhuǎn)換速率： 20 V/µs
-3db帶寬： 10MHz
工作溫度： -40°C ~ 85°C
電流供應(yīng)（主 IC）： 4.1mA
電壓 - 電源，單路/雙路(±)： 5 V ~ 15 V
板類型： 完全填充
已供物品： 板
已用 IC / 零件： AD8251
AD8251
Rev. B | Page 17 of 24
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
A1
A0
Gain
VS
Low
1
VS
Low
High
2
VS
High
Low
4
VS
High
8
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8251 can be set using WR as a latch,
allowing other devices to share A0 and A1.
shows a
schematic using this method, known as latched gain mode. The
AD8251 is in this mode when
WR is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0 and A1
are read on the downward edge of the WR signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table in
for more information on these gain changes.
+15V
–15V
A0
A1
WR
+IN
–IN
10
μF0.1F
10
μF0.1F
DGND
REF
AD8251
A0
A1
WR
+5V
0V
G = PREVIOUS
STATE
G = 8
+
–
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8.
06
28
7-
05
2
Figure 53. Latched Gain Mode, G = 8
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
A1
A0
Gain
High to low
Low
Change to 1
High to low
Low
High
Change to 2
High to low
High
Low
Change to 4
High to low
High
Change to 8
Low to low
No change
Low to high
No change
High to high
No change
1 X = don’t care.
On power-up, the AD8251 defaults to a gain of 1 when in latched
gain mode. In contrast, if the AD8251 is configured in transparent
gain mode, it starts at the gain indicated by the voltage levels on
A0 and A1 at power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, tSU, before the downward edge of WR
latches in the gain. Similarly, they must be held for a minimum
hold time of tHD after the downward edge of WR to ensure that
the gain is latched in correctly. After tHD, A0 and A1 can change
logic levels, but the gain does not change (until the next
downward edge of WR). The minimum duration that WR can
be held high is t WR-HIGH, and the minimum duration that WR
can be held low is t WR-LOW. Digital timing specifications are
listed in
The time required for a gain change is
dominated by the settling time of the amplifier. A timing
diagram is shown in
.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8251. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog portions
of the board. Pull-up or pull-down resistors should be used to
provide a well-defined voltage at the A0 and A1 pins.
A0, A1
WR
tSU
tHD
tWR-HIGH
tWR-LOW
0
62
87
-0
53
Figure 54. Timing Diagram for Latched Gain Mode
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