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| 型號： | AD8251-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD8251 PGA |
| 標準包裝： | 1 |
| 系列： | iCMOS® |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類型： | 儀表 |
| 輸出類型： | 單端 |
| 轉(zhuǎn)換速率： | 20 V/µs |
| -3db帶寬： | 10MHz |
| 工作溫度： | -40°C ~ 85°C |
| 電流供應(yīng)（主 IC）： | 4.1mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 15 V |
| 板類型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD8251 |
AD8251
Rev. B | Page 19 of 24
REFERENCE TERMINAL
The reference terminal, REF, is at one end of a 10 kΩ resistor
(see Figure 51). The instrumentation amplifier output is referenced
to the voltage on the REF terminal; this is useful when the output
signal needs to be offset to voltages other than its local analog
ground. For example, a voltage source can be tied to the REF
pin to level shift the output so that the AD8251 can interface
with a single-supply ADC. The allowable reference voltage
range is a function of the gain, common-mode input, and
supply voltages. The REF pin should not exceed either +VS
or VS by more than 0.5 V.
For best performance, especially in cases where the output is
not measured with respect to the REF terminal, source imped-
ance to the REF terminal should be kept low because parasitic
resistance can adversely affect CMRR and gain accuracy.
INCORRECT
AD8251
VREF
CORRECT
AD8251
OP1177
+
–
VREF
0
628
7-
0
56
Figure 57. Driving the Reference Pin
COMMON-MODE INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8251 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8251 experience a combination of both the gained
signal and the common-mode signal. This combined signal
can be limited by the voltage supplies even when the individual
the allowable common-mode input voltage ranges for various
output voltages, supply voltages, and gains.
LAYOUT
Grounding
In mixed-signal circuits, low level analog signals need to be
isolated from the noisy digital environment. Designing with the
AD8251 is no exception. Its supply voltages are referenced to an
analog ground. Its digital circuit is referenced to a digital ground.
Although it is convenient to tie both grounds to a single ground
plane, the current traveling through the ground wires and PCB
can cause errors. Therefore, use separate analog and digital
ground planes. Analog and digital ground should meet at one
point only: star ground.
The output voltage of the AD8251 develops with respect to the
potential on the reference terminal. Take care to tie REF to the
appropriate local analog ground or to connect it to a voltage that
is referenced to the local analog ground.
Coupling Noise
To prevent coupling noise onto the AD8251, follow these
guidelines:
Do not run digital lines under the device.
Run the analog ground plane under the AD8251.
Shield fast switching signals with digital ground to avoid
radiating noise to other sections of the board, and never
run them near analog signal paths.
Avoid crossover of digital and analog signals.
Connect digital and analog ground at one point only
(typically under the ADC).
Use large traces on the power supply lines to ensure a low
impedance path. Decoupling is necessary; follow the
guidelines listed in the Power Supply Regulation and
Bypassing section.
Common-Mode Rejection
The AD8251 has high CMRR over frequency, giving it greater
immunity to disturbances, such as line noise and its associated
harmonics, in contrast to typical instrumentation amplifiers
whose CMRR falls off around 200 Hz. The typical instrumentation
amplifiers often need common-mode filters at their inputs to
compensate for this shortcoming. The AD8251 is able to reject
CMRR over a greater frequency range, reducing the need for
input common-mode filtering.
Careful board layout maximizes system performance. To
maintain high CMRR over frequency, lay out the input traces
symmetrically. Ensure that the traces maintain resistive and
capacitive balance; this holds for additional PCB metal layers
under the input pins and traces. Source resistance and capaci-
tance should be placed as close to the inputs as possible. Should
a trace cross the inputs (from another layer), it should be routed
perpendicular to the input traces.
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