參數(shù)資料
型號(hào)： AD818
廠商： Analog Devices, Inc.
英文描述： Low Cost, Low Power Video Op Amp(低成本,低功耗視頻運(yùn)放)
中文描述： 低成本，低功耗視頻運(yùn)算放大器（低成本，低功耗視頻運(yùn)放）
文件頁(yè)數(shù)： 11/12頁(yè)
文件大?。?/td> 535K
代理商： AD818
AD818
REV. A
–11–
AD829
100
0.47μF
0.01μF
–V
S
0.47μF
0.01μF
+V
S
SHORT, DIRECT
CONNECTION TO
TEKTRONIX TYPE 11402
OSCILLOSCOPE PREAMP
INPUT SECTION
15pF
1M
SETTLING
OUTPUT
2
HP2835
ERROR AMPLIFIER
V
ERROR
OUTPUT
×
10
1.9k
100
AD818
0.01μF
–V
S
0.01μF
2.2μF
+V
S
2.2μF
10pF
SCOPE PROBE
CAPACITANCE
TEKTRONIX P6201
FET PROBE TO
TEKTRONIX TYPE 11402
OSCILLOSCOPE
PREAMP INPUT SECTION
500
5–18pF
DEVICE
UNDER
TEST
NOTE:
USE CIRCUIT BOARD
WITH GROUND PLANE
FALSE
SUMMING
NODE
NULL
ADJUST
1k
100
1k
50
COAX
CABLE
TTL LEVEL
SIGNAL
GENERATOR
50Hz
OUTPUT
2
13
1, 14
7, 8
DIGITAL
GROUND
ANALOG
GROUND
0 TO ±10V
POWER
SUPPLY
EI&S
DL1A05GM
MERCURY
RELAY
ERROR
SIGNAL
OUTPUT
500
50
2
3
5
6
4
7
2
HP2835
2
3
6
7
4
Figure 37. Settling Time Test Circuit
DIFFE RE NT IAL LINE RE CE IVE R
T he differential receiver circuit of Figure 39 is useful for many
applications from audio to video. It allows extraction of a low
level signal in the presence of common-mode noise. As shown
in Figure 40, the AD818 provides this function with only
10 nV/
√
Hz
noise at the output.
V
OUT
2pF
DIFFERENTIAL
INPUT
+5V
–5V
OUTPUT
AD818
0.01μF
2.2μF
2
3
6
4
7
0.01μF
2.2μF
2pF
1k
1k
1k
1k
Figure 39. Differential Line Receiver
AAAA
200
V
10n
s
200m
A
A
10
90
100
0%
AAAA
AA
AAA
AAA
AAA
2V
AAA
AAAA
A
AAA
1V
20ns
Figure 40. Performance of Line Receiver, R
L
= 150
,
G = +2
AD818 SE T T LING T IME
Settling time is comprised primarily of two regions. T he first is
the slew time in which the amplifier is overdriven, where the
output voltage rate of change is at its maximum. T he second is
the linear time period required for the amplifier to settle to
within a specified percent of the final value.
Measuring the rapid settling time of AD818 (45 ns to 0.1% and
80 ns to 0.01%—10 V step) requires applying an input pulse
with a very fast edge and an extremely flat top. With the AD818
configured in a gain of –1, a clamped false summing junction
responds when the output error is within the sum of two diode
voltages (approximately 1 volt). T he signal is then amplified 20
times by a clamped amplifier whose output is connected directly
to a sampling oscilloscope.
A High Performance Video Line Driver
T he buffer circuit shown in Figure 38 will drive a back-termi-
nated 75
video line to standard video levels (1 V p-p) with
0.1 dB gain flatness to 55 MHz with only 0.05
°
and 0.01%
differential phase and gain at the 3.58 MHz NT SC subcarrier
frequency. T his level of performance, which meets the require-
ments for high-definition video displays and test equipment, is
achieved using only 7 mA quiescent current.
+15V
V
IN
–15V
AD818
0.01μF
2.2μF
2
3
6
4
7
0.01μF
2.2μF
Rt
75
Rbt
75
75
Rt
75
1k
1k
Figure 38. Video Line Driver
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