參數(shù)資料
型號: AD8178ABPZ
廠商: Analog Devices Inc
文件頁數(shù): 24/40頁
文件大?。?/td> 0K
描述: IC VIDEO CROSSPOINT SWIT 676BGA
標準包裝: 1
功能: 視頻交叉點開關
電路: 3 x 16:5
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V,±2.5V
電流 - 電源: 460mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 676-BGA
供應商設備封裝: 676-BGA(27x27)
包裝: 管件
AD8178
Rev. 0 | Page 30 of 40
The AD8178 is adjusted such that its gain is correct when
driven by a back-terminated Cat-5 cable (25 Ω effective
impedance to ground at each input pin, or 100 Ω differential
source impedance across pairs of input pins). If a different
source impedance is presented, the differential gain of the
AD8178 input receiver can be calculated as
S
DM
R
G
+
=
5
.
2
05
.
5
where RS is the effective impedance to ground at each input pin.
When operating with a differential input, care must be taken to
keep the common mode, or average, of the input voltages within
the linear operating range of the AD8178 receiver. For the AD8178
receiver, this common-mode range can extend rail-to-rail, provided
the differential signal swing is small enough to avoid forward
biasing the ESD diodes (it is safest to keep the common mode plus
differential signal excursions within the supply voltages of the part).
The input voltage of the AD8178 is linear for ±0.5 V of differen-
tial input voltage difference (this limitation is primarily due to
the ability of the output to swing close to the rails because the
differential gain through the part is +4). Beyond this level, the
signal path saturates and limits the signal swing. This is not
a desired operation because the supply current increases and
the signal path is slow to recover from clipping. The absolute
maximum allowed differential input signal is limited by long-
term reliability of the input stage. The limits in the Absolute
Maximum Ratings section should be observed to avoid degrading
device performance permanently.
AC Coupling of Inputs
It is possible to ac-couple the inputs of the AD8178 receiver
so that bias current does not need to be supplied externally.
A capacitor in series with the inputs to the AD8178 creates
a high-pass filter with the input impedance of the device. This
capacitor needs to be large enough that the corner frequency
includes all frequencies of interest.
Single-Ended Input
The AD8178 input receiver can be driven single-endedly
(unbalanced). Single-ended inputs apply a component of
common-mode signal to the receiver inputs, which is then
rejected by the receiver (see the Specifications section for
common-mode-to-differential-mode ratio of the part).
The single-ended input resistance, RIN, differs from the
differential input impedance, and is equal to
)
(
2
1
F
G
F
G
IN
R
+
×
=
with RG and RF, as shown in Figure 49.
Note that this value is smaller than the differential input
resistance, but it is larger than RG. The difference is due to the
component of common-mode level applied to the receiver by
single-ended inputs. A second, smaller component of input
resistance (RCM, also shown in Figure 49) is present across the
inputs in both single-ended and differential operation.
In single-ended operation, an input is driven, and the undriven
input is often tied to midsupply or ground. Because signal-
frequency current flows at the undriven input, such input
should be treated as a signal line in the board design.
For example, to achieve best dynamic performance, the undriven
input should be terminated with an impedance matching that seen
by the part at the driven input.
Differential Output
Benefits of Differential Operation
The AD8178 has a fully differential switch core with differential
outputs. The two output voltages move in opposite directions,
with a differential feedback loop maintaining a fixed output
stage differential gain of +2 through the core. This differential
output stage provides improved crosstalk cancellation due to
parasitic coupling from one output to another being equal and
out of phase. Additionally, if the output of the device is utilized
in a differential design, then noise, crosstalk, and offset voltages
generated on-chip that are coupled equally into both outputs
are cancelled by the common-mode rejection ratio of the next
device in the signal chain. By utilizing the AD8178 outputs in
a differential application, the best possible noise and offset
specifications can be realized.
Differential Gain
The specified signal path gain of the AD8178 refers to its
differential gain. For the AD8178, the gain of +4 means that the
difference in voltage between the two output terminals is equal
to four times the difference between the two input terminals.
Common-Mode Gain
The common-mode, or average voltage pairs of output signals
is set by the voltage on the VOCM_CMENCOFF pin when
common-mode encoding is off (CMENC is a logic low), or by
the voltage on the VOCM_CMENCON pin when common-mode
encoding is on (CMENC is a logic high). Note that in the latter
case, VCOM_CMENCON sets the overall common mode of
RGB triplets of differential outputs, and the individual common
mode of each RGB output is free to change. VCOM_CMENCON
and VCOM_CMENCOFF are typically set to midsupply (often
ground) but can be moved approximately ±0.5 V to accommodate
cases where the desired output common-mode voltage may not
be midsupply (as in the case of unequal split supplies). Adjusting
the output common-mode voltage beyond ±0.5 V can limit differ-
ential swing internally below the specifications on the data sheet.
The overall common mode of the output voltages follow the
voltage applied to VOCM_CMENCON or VCOM_CMENCOFF,
implying a gain of +1. Likewise, sync-on common-mode signaling
is carried through the AD8178 (CMENC must be in its high
state), implying a gain of +1 for this path as well.
The common-mode reference pins are analog signal inputs,
common to all output stages on the device. They require only
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