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參數(shù)資料
| 型號： | AD8178ABPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/40頁 |
| 文件大小： | 0K |
| 描述： | IC VIDEO CROSSPOINT SWIT 676BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 視頻交叉點開關(guān) |
| 電路： | 3 x 16:5 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.5V |
| 電流 - 電源： | 460mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-BGA（27x27） |
| 包裝： | 管件 |
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AD8178
Rev. 0 | Page 28 of 40
For a practical example, refer to Figure 48. Note that the output
pulses have been shifted slightly with respect to each other for
clarity.
1.4V
NEGATIVE
PHASE
POSITIVE
PHASE
VBLK = 0V
VOCM_CMENCOFF = 0.7V
0V
06
60
8-
02
3
Figure 48. Output at the AD8178 Pins for 0 V to 0.7 V Input Differential Pulse,
VBLK = 0 V, VOCM_CMENCOFF = 0.7 V
The input to the AD8178 is a differential pulse with a low level
of 0 V and a high level of 0.7 V. VBLK is set to 0 V, and VOCM_
CMENCOFF is set to 0.7 V. With this choice of values, the positive
and negative output phases are overlapped, with the positive phase
ranging from 0 V to 1.4 V, and the negative phase ranging from
1.4 V to 0 V, respectively. The supplies are set to +3 V/2 V to be in
compliance with output headroom requirements.
The voltage on the positive output phase for a 0 V differential
input is equal to the voltage on VBLK, for all cases when VBLK
and VOCM_CMENCOFF differ by more than ±100 mV.
PROGRAMMING
The AD8178 has two options for changing the programming of
the crosspoint matrix. In the first option, a serial word of 45 bits
can be provided that updates the entire matrix each time. The
second option allows for changing the programming of a single
output using a parallel interface. The serial option requires
fewer signals, but more time (clock cycles), for changing the
programming; the parallel programming technique requires more
signals, but it allows for changing a single output at a time,
therefore requiring fewer clock cycles.
Serial Programming Description
The serial programming mode uses the device pins CS, CLK,
SERIN, UPDATE, and SER/PAR. The first step is to enable the
CLK on by pulling CS low. Next, SER/PAR is pulled low to
enable the serial programming mode. The parallel clock WE
should be held high during the entire serial programming
operation.
The UPDATE signal should be high during the time that data
is shifted into the serial port of the device. Although the data still
shifts in when UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as
defined by the shifting data.
The data at SERIN is clocked in at every falling edge of CLK.
A total of 45 bits must be shifted in to complete the programming.
A total of five bits must be supplied for each of the five RGB
output channels: an output enable bit (D4) and four bits (D3
to D0) that determine the input channel.
If D4 is low (output disabled), the four associated bits (D3 to
D0) do not matter because no input is switched to that output.
A sequence of five bits at Logic 0 must be supplied in between
each D4 to D0 group of bits for padding purposes. There is a total
of four such sequences of zeros.
The most significant output address data is shifted in first, with
the enable bit (D4) shifted in first, followed by the input address
(D3 to D0) entered sequentially with D3 first and D0 last. The first
sequence of five bits at Logic 0 is shifted in next. Each remaining
output is programmed sequentially in a similar fashion, until
the least significant output address data is shifted in. Note that
the last D4 to D0 group is not followed by a corresponding group
of five zeros. At this point, UPDATE can be taken low, which
causes the programming of the device according to the data that
was just shifted in. The UPDATE latches are asynchronous; and
when UPDATE is low, they are transparent.
If more than one AD8178 device is to be serially programmed
in a system, the SEROUT signal from one device can be connected
to the SERIN of the next device to form a serial chain. All of the
CLK, UPDATE, and SER/PAR pins should be connected in parallel
and operated as described previously. The serial data is input to
the SERIN pin of the first device of the chain, and it ripples
through to the last. Therefore, the data for the last device in the
chain should come at the beginning of the programming sequence.
The length of the programming sequence is 45 bits times the
number of devices in the chain. CS gates the CLK and UPDATE
signals, so that when CS is held high, both CLK and UPDATE are
held in their inactive high state. When CS is held low, both CLK
and UPDATE function normally.
Parallel Programming Description
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows the modification of a single
output or more at a time. Because this modification takes only
one WE/UPDATE cycle, significant time savings can be realized
by using parallel programming.
One important consideration in using parallel programming is
that the RST signal does not reset all registers in the AD8178.
When taken low, the RST signal only sets each output to the
disabled state. This is helpful during power-up to ensure that
two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device generally
have random data, even though the RST signal is asserted. If
parallel programming is used to program one output, then that
output is properly programmed, but the rest of the device has
a random program state, depending on the internal register content
at power-up. Therefore, when using parallel programming, it is
essential that all outputs be programmed to a desired state after
power-up. This ensures that the programming matrix is always
in a known state. From then on, parallel programming can be
used to modify a single output or more at a time.
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