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參數資料
| 型號： | AD8170AR |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX W/AMP BUFFERED 8-SOIC |
| 標準包裝： | 98 |
| 應用： | 帶放大器的多路復用器 |
| 電源電壓： | ±4 V ~ 6 V |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
–3–
REV. 0
AD8170/AD8174
AD8170A/AD8174A
Parameter
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Input Resistance
(+) Switch Input
1.7
M
(–) Buffer Input
100
Input Capacitance
Channel Enabled (R Package)
1.1
pF
Channel Disabled (R Package)
1.1
pF
Input Voltage Range
±3.3
V
Input Common-Mode Rejection Ratio
+CMRR,
V
CM = 1 V
51
56
dB
–CMRR,
V
CM = 1 V
50
52
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 k, TMIN–TMAX
±4.0
±4.26
V
RL = 150 , TMIN–TMAX
±3.5
±4.0
V
Output Current
RL = 10
50
mA
Short Circuit Current
180
mA
Output Resistance
Enabled
10
m
Disabled (AD8174)
10
M
Output Capacitance
Disabled (AD8174)
7.5
pF
POWER SUPPLY
Operating Range
±4
±6V
Power Supply Rejection Ratio
+PSRR
+VS = +4.5 V to +5.5 V, –VS = –5 V
58
66
dB
TMIN–TMAX
55
dB
Power Supply Rejection Ratio
–PSRR
–VS = –4.5 V to –5.5 V, +VS= +5 V
52
58
dB
TMIN–TMAX
50
dB
Quiescent Current
All Channels “ON”, TMIN–TMAX
8.7/9.7
11/13
mA
AD8174 Disabled, TMIN–TMAX
4.1
5
mA
AD8174 Shutdown, TMIN–TMAX
1.5
2.5
mA
OPERATING TEMPERATURE RANGE
–40
+85
°C
NOTES
1Shutdown (SD) and ENABLE pins are grounded (AD8174). IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc. SELECT (A0 or A1 for AD8174) input is
driven with 0 V to +5 V pulse. Measure transition time from 50% of SELECT (A0 or A1) input value (+2.5 V) and 10% (or 90%) of the total output voltage transi-
tion from IN0 (or IN2) channel voltage (+0.5 V) to IN1 (or IN3 = –0.5 V) or vice versa.
2AD8174 only. Shutdown (SD) pin is grounded. ENABLE pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines
which channel is activated (i.e., if A0 = Logic 0 and A1 = Logic 1, then IN2 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-
sure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5,
t
OFF is the disable time,
t
ON is the enable time.
3AD8174 only. ENABLE pin is grounded. Shutdown (SD) pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines
which channel is activated (i.e., if A0 = Logic 1 and A1 = Logic O, then IN1 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-
sure transition time from 50% of SD pulse (+2.5 V) to 90% of the total output voltage change. In Fig ure 6,
t
OFF is the shutdown assert time ,
t
ON is the shutdown
release time.
4All inputs are grounded. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT
(A0 or A1) pulse increases the glitch magnitude due to coupling via the ground plane.
5Bandwidth of the multiplexer is dependent upon the resistor feedback network. Refer to Table III for recommended feedback component values, which give the best
compromise between a wide and a flat frequency response.
6Select input(s) that is (are) not being driven (i.e., if SELECT is Logic 1, activated input is IN1; in AD8174, if A0 = Logic 0, A1 = Logic 1, activated input is IN2).
Drive all other inputs with VIN = 0.707 V rms, and monitor output at f = 5 MHz and 30 MHz; RL = 100
(see Figure 13).
7AD8174 only. Shutdown (SD) pin is grounded. Mux is disabled, (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with V
IN = 0.354 V rms. Out-
put is monitored at f = 5 MHz and 30 MHz; RL = 100
. In this mode, the output impedance of the disabled mux is very high (typ 10 M), and the signal couples
across the package; the load impedance and the feedback network determine the crosstalk. For instance, in a closed-loop gain of +1, r OUT
10 M
, in a gain of +2
(RF = RG = 549
), r
OUT = 1.1 k
(see Figure 14).
8AD8174 only. ENABLE pin is grounded. Mux is shutdown (i.e., SD = Logic 1), and all inputs are driven simultaneously with V
IN = 0.354 V rms. Output is moni-
tored at f = 5 MHz and 30 MHz; RL = 100
. (see Figure 14). The mux output impedance in shutdown mode is the same as the disabled mux output impedance.
9For Gain Accuracy expression, refer to Equation 4.
Specifications subject to change without notice.
Table I. AD8170 Truth Table
SELECT
VOUT
0
IN0
1
IN1
Table II. AD8174 Truth Table
A0
A1
ENABLE
SD
VOUT
0
IN0
1
0
IN1
0
1
0
IN2
1
0
IN3
X
1
0
HIGH Z, IS = 4.1 mA
X
1
HIGH Z, IS = 1.5 mA
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