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參數(shù)資料
| 型號： | AD8155ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX/DEMUX DUAL BUFFER 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 多路復(fù)用器/多路分解器 |
| 電路： | 2 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.6 V ~ 3.6 V |
| 電流 - 電源： | 735mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD8155
Rev. 0 | Page 16 of 36
Table 6. Features Available Through Toggle Pin or Serial Control
Feature
Pin Control
Serial Control
Switch Features
BICAST
One pin
One bit
A/B Lane Select
Two pins
Two bits
Loopback
Three pins
Three bits
Rx Features
EQ Levels
Two settings
10 settings
N/P Swap
Not available
Available
Squelch
Enabled
Three bits
Tx Features
Programmable Output Levels
±400 mV diff fixed1
±200 mV diff/±300 mV diff/±400 mV diff/±600 mV diff
PE Levels
Two settings
>7 settings
1 ±400 mV diff indicates a 400 mV amplitude signal measured between two differential nodes. The voltage swing at differential I/O pins is described in this data sheet
both in terms of the differentially measured voltage range (±400 mV diff, for example) and in terms of peak-to-peak differential swing, denoted as mV p-p diff. An
output level setting of ±400 mV diff delivers a differential peak-to-peak output voltage of 800 mV p-p diff.
THE SWITCH
(MUX/DEMUX/UNICAST/BICAST/LOOPBACK)
The mux and demux functions of the AD8155 can be controlled
either with the toggle pins or through the register map. The
multiplexer path switches received data from Input Port A or
Input Port B to Output Port C. The SEL[1:0] pins allow switching
lanes independently. The demultiplexer path switches received
data from Input Port C to Output Port A, Output Port B, or (if
bicast mode is enabled) to both Output Port A and Output Port B.
Table 7. Port Selection and Configuration with All
Loopbacks Disabled
BICAST
SELx
Output
Port A
Output
Port B
Output
Port C
0
Ix_C[1:0]
Idle
Ix_A[1:0]
0
1
Idle
Ix_C[1:0]
Ix_B[1:0]
1
0
Ix_C[1:0]
Ix_A[1:0]
1
Ix_C[1:0]
Ix_B[1:0]
When the device is in unicast mode, the output lanes on either
Port A or Port B are in an idle state. In the idle state, the
transmitter output current is set to 0, and the P and N sides of
the lane are pulled up to the output termination voltage through
the on-chip termination resistors. To save power, the unused
receiver automatically disables.
The AD8155 supports port-level loopback, illustrated in Figure 36.
The loopback control pins override the lane select (SEL[1:0])
and bicast control (BICAST) pin settings at the port level. In serial
control mode, Bits [6:4] of Register 0x01 control loopback and
are equivalent to asserting Pin LB_A, Pin LB_B, and Pin LB_C.
Table 8 summarizes the different loopback configurations.
The loopback feature is useful for system debug, self-test, and
initialization, allowing system ASICs to compare Tx and Rx
data sent over a single bidirectional link. Loopback can also be
used to configure the device as a two- to six-lane receive
equalizer or backplane redriver.
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| AD8155ACPZ-R7 | 功能描述:IC MUX/DEMUX DUAL BUFFER 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:XStream™ 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
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