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參數(shù)資料
| 型號： | AD8152JBP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 34X34 256BGA |
| 標(biāo)準包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點開關(guān) |
| 電路： | 1 x 34:34 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.25 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 256-SBGA（27x27） |
| 包裝： | 托盤 |
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REV. A
–22–
AD8152
The variety of supply configurations cause the need for a supply
agile digital control circuitry. This is done by a programmable
logic device (PLD), which provides instructions to the AD8152.
The PLD supply is typically tied with jumpers across the AD8152’s
VCC and VEE supplies (Jumpers J3 and J4). The PLD is addressed
from the PC by way of digital isolators. These couplers isolate
PC levels from the PLD and allow for any level shifting. If
desired, the user can drive the PLD supply separately as long as
the VEE of the AD8152 and the PLD are tied together (remove
Jumper J3 and leave J4 installed). This allows one to measure
the AD8152 only supply current, for example.
Board Construction or Stack-Up
Figure 11 is a picture of AD8152 evaluation board stack-up from
top to bottom. The layer stack-up has been made symmetrical
to avoid board warpage during manufacture. The microstrip
layout and dimensions are shown in Figure 12. The microstrip
trace width was chosen to be 8 mils. This allows relative ease in
routing through the BGA rows that are 50 mils (1.27 mm) apart.
The outer two out of four rows of high speed signals are routed on
top of the PCB, while the inner two rows are via holed to the
board’s opposite side and then routed outward. Wider microstrip
is desirable for reducing eye height loss versus long traces; how-
ever, the routing will be more difficult as the AD8152 is approached.
The wide microstrip would have to be necked down in width in
order to be routed into the BGA. The necking will increase trace
impedance and therefore induce more signal reflection problems.
MICROSTRIP TRACES
BGA CORNER OUTLINE
VIA HOLE
(GRAY)
CHIP CAPACITOR
(805) SIZE
Figure 13. BGA Corner Capacitor Layout
Figure 12. Cross-Sectional Layout and Dimensioning (To Scale) of Differential
During the layout of the differential microstrip, a software tool
snaps the distance between the two traces to be a constant. If
the distance is not kept constant, impedance variations will
result. These fluctuations can be measured by time domain
reflectometry (TDR).
EXTRA ADDED INDUCTANCE
Figure 14. Poor Capacitor Layout
Bypass Capacitor Layout
The AD8152 8-layer PCB takes advantage of buried interlayer
capacitance. The VEE to VCC planes are placed in the very middle
of the board to make the highest value capacitor. The 4 mil
(0.102 mm) dielectric spacing between VCC/VEE yields 26 nF
of capacitance. Each AD8152 supply pin is directly connected to
its supply plane through a via hole beneath the BGA ball. The
via hole size for a BGA supply pin is slightly bigger than a signal
via. This is to reduce the inductance of the connection, and it
also happens to be a compact layout.
For the chip capacitors, the via holes are placed directly in the
middle of the mounting area and made as large as possible, i.e.,
greater than or equal to 35 mils (0.89 mm). This is to minimize
inductance as much as possible. By minimizing inductance, the
performance of the capacitor or impedance versus frequency
response is not greatly diminished. Note that chip capacitors
will work up to only about 300 MHz.
Figure 14 is an example of a bypass capacitor layout that should
be avoided in any high speed printed circuit board. This layout
connects the chip capacitor mounting pads to small via holes
through a skinny PCB trace. This amounts to four extra inductors
added to the capacitor, two largely from the skinny surface traces
and two from small via holes. Inductance is also variable with
copper thickness and attachment method to power plane. Thermal
relief for soldering purposes also adds unwanted inductance and
should be avoided.
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