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參數(shù)資料
| 型號： | AD8128ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 0K |
| 描述： | IC RECEIVER LINE EQUAL 8LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 接收器 |
| 驅(qū)動器/接收器數(shù)： | 0/1 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 8-LFCSP-VD（3x3） |
| 包裝： | 帶卷 (TR) |
AD8128
Rev. 0 | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage
±5.5 V
Input Voltage
±VS
VPEAK and VGAIN Control Pins
3 V to +VS
VOFFSET Control Pins
±VS
Operating Temperature Range
40°C to +85°C
Storage Temperature Range
65°C to +125°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
8-Lead LFCSP
77
14
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8128 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8128. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for the output. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through-holes, ground, and power planes reduces
the θJA. The exposed paddle on the underside of the package
must be soldered to a pad on the PCB surface, which is
thermally connected to a copper plane to achieve the specified θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead LFCSP
(48.5°C/W) on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. Extra thermal relief is required for operation at
high supply voltages.
3.0
0
–30
–40
–10
–20
10
030
20
50
40
70
60
90
80
110
100
130
120
05
69
9-
0
20
AMBIENT TEMPERATURE (°C)
MA
XIMU
M
P
O
WER
D
ISS
IP
A
TI
O
N
(
W
)
2.5
2.0
1.5
1.0
0.5
Figure 2. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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