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參數(shù)資料
| 型號： | AD8124ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HS RCVR EQUALIZER 40VFQFN |
| 標準包裝： | 750 |
| 類型： | 接收器 |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 電源電壓： | ±4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
AD8124
Rev. 0 | Page 13 of 16
USING THE AD8124 WITH COAXIAL CABLE
The VPOLE control allows the AD8124 to be used with other
types of cable, including coaxial cable. Figure 17 presents the
recommended settings for VPEAK, VPOLE, and VGAIN when the
AD8124 is used with good quality 75 Ω video cable. Figure 23
shows how to derive VPOLE and VGAIN from VPEAK in a coaxial
cable application where VPEAK originates from a low-Z source.
20
5.11k
20k
VPEAK
–5V
+5V
24.3k
47.5k
1.16k
VGAIN ≈ 1.06 × VPEAK – 0.62V
VPOLE ≈ 0.76 × VPEAK – 0.41V
10k
1.24k
0
960
1-
0
23
Figure 23. Deriving VPOLE and VGAIN from VPEAK with Low-Z Source for the Coaxial Cable
The op amp in the circuit that develops VGAIN is required to insert
the offset of 0.62 V with a gain from VPEAK to VGAIN that is close to
unity. A passive offset circuit requires an offset injection voltage
that is much larger in magnitude than the available 5 V supply.
Clearly, the VGAIN control voltage can also be developed
independently.
The AD8124 differential input can accept signals carried over
unbalanced cable, as shown in Figure 24, for an unbalanced
75 Ω coaxial cable termination.
09
60
1-
0
30
75
INPUT FROM
75 CABLE
AD8124
INPUT STAGE
Figure 24. Terminating a 75 Ω Cable
DRIVING 75 Ω VIDEO CABLE WITH THE AD8124
When the RGB outputs must drive a 75 Ω line rather than a
high impedance load, an additional gain of two is required to
make up for the double termination loss (75 Ω source and load
terminations). There are two options available for this.
One option is to place the additional gain of 2 at the drive end
by using the AD8148 triple differential driver to drive the cable.
The AD8148 has a fixed gain of 4 instead of the usual gain of 2
and thereby provides the required additional gain of 2 without
having to add additional amplifiers to the signal chain. The
AD8148 also contains sync-on-common-mode encoding. If
sync-on-common-mode is not required, it can be deactivated
on the AD8148 by connecting its sync level input to ground.
The other option is to include a triple gain-of-2 buffer, such as the
ADA4862-3, on the AD8124 RGB outputs, as shown in Figure 25
for one channel (power supplies not shown). The ADA4862-3
provides the gain of 2 that compensates for the double-
termination loss.
ONE VIDEO
OUTPUT
FROM AD8124
ONE CHANNEL OF ADA4862-3
75
75
500
Z0 = 75
096
01
-02
5
Figure 25. Using the ADA4862-3 on AD8124 Outputs
DRIVING A CAPACITIVE LOAD
When driving a high impedance capacitive input, it is necessary
to place a small series resistor between each of the three AD8124
video outputs and the load to buffer the input capacitance of the
device being driven. Clearly, the resistor value must be small
enough to preserve the required bandwidth.
POWER SUPPLY FILTERING
External power supply filtering between the system power supplies
and the AD8124 is recommended in most applications to prevent
supply noise from contaminating the received signal as well as
to prevent unwanted feedback through the supplies that may
cause instability. Figure 26 shows that the AD8124 power supply
rejection decreases with increasing frequency. These plots are
for the lowest control settings and shift upward as the peaking
is increased.
0
9601
-026
–60
–50
–40
–30
–20
–10
0
10
+PSRR
–PSRR
100k
1M
10M
100M
FREQUENCY (Hz)
P
S
RR
(
d
B)
VGAIN =0V
VPEAK =0V
VPOLE =0V
Figure 26. PSRR vs. Frequency
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