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參數(shù)資料
| 型號： | AD8124ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 0K |
| 描述： | IC HS RCVR EQUALIZER 40VFQFN |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 接收器 |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 電源電壓： | ±4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
AD8124
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage
11 V
Power Dissipation
See Figure 2
Input Voltage (Any Input)
VS 0.3 V to VS+ + 0.3 V
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +85°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for the device soldered in a circuit board in still air.
Table 3. Thermal Resistance with the Underside Pad
Connected to the Plane
Package Type/PCB Type
θJA
Unit
40-Lead LFCSP/4-Layer
29
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8124 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8124. Exceeding a junction temperature
of 175°C for an extended time can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipation due to each load
current is calculated by multiplying the load current by the
voltage difference between the associated power supply and the
output voltage. The total power dissipation due to load currents
is then obtained by taking the sum of the individual power
dissipations. RMS output voltages must be used when dealing
with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduces the θJA. The exposed paddle on the
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a solid plane (usually the
ground plane) to achieve the specified θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 40-lead LFCSP
(29°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θJA values are approximations.
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
M
A
XI
M
U
M
PO
W
ER
D
ISSI
PA
T
IO
N
(
W
)
1
2
3
4
5
6
7
09
60
1-
00
3
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
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