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參數(shù)資料
| 型號(hào)： | AD8118ABPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 600 MHz, 32 】 32 Buffered Analog Crosspoint Switch |
| 中文描述： | 32-CHANNEL, CROSS POINT SWITCH, PBGA304 |
| 封裝： | 31 X 31 MM, ROHS COMPLIANT, MO-192BAN-2, BGA-304 |
| 文件頁(yè)數(shù)： | 31/36頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | AD8118ABPZ |
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AD8117/AD8118
operation, as there is a common-mode to differential gain
conversion that becomes greater at higher frequencies.
During operation of the AD8117/AD8118, transient currents
flow into the VOCM net from the amplifier control loops.
Although the magnitude of these currents are small (10 μA to
20 μA per output), they can contribute to crosstalk if they flow
through significant impedances. Driving VOCM with a low
impedance, low noise source is desirable.
Power Dissipation
Calculation of Power Dissipation
8
Rev. A | Page 31 of 36
4
15
85
M
AMBIENT TEMPERATURE (°C)
T
J
= 150°C
7
6
5
25
35
45
55
65
75
0
Figure 70. Maximum Die Power Dissipation vs. Ambient Temperature
The curve in Figure 70 was calculated from
JA
AMBIENT
T
MAX
θ
JUNCTION
MAX
D
T
P
=
,
,
(1)
As an example, if the AD8117/AD8118 is enclosed in an envi-
ronment at 45°C (T
A
), the total on-chip dissipation under all
load and supply conditions must not be allowed to exceed 7.0 W
When calculating on-chip power dissipation, it is necessary to
include the rms current being delivered to the load, multiplied
by the rms voltage drop on the AD8117/AD8118 output
devices. For a sinusoidal output, the on-chip power dissipation
due to the load can be approximated by
(
UTPUT
O
POS
OUTPUT
D
V
V
P
,
For nonsinusoidal output, the power dissipation should be
calculated by integrating the on-chip voltage drop multiplied by
the load current over one period.
The user can subtract the quiescent current for the Class AB
output stage when calculating the loaded power dissipation. For
each output stage driving a load, subtract a quiescent power
according to
(
)
NEG
POS
OUTPUT
DQ
V
V
P
,
)
RMS
OUTPUT
RMS
I
,
,
×
=
QUIESCENT
OUTPUT
I
,
×
=
where
I
OUTPUT, QUIESCENT
= 1.65 mA for each single-ended output pin.
For each disabled output, the quiescent power supply current in
VPOS and VNEG drops by approximately 9 mA.
QNPN
QPNP
V
NEG
V
POS
V
OUTPUT
I
OUTPUT
I
OUTPUT, QUIESCENT
I
OUTPUT, QUIESCENT
0
Figure 71. Simplified Output Stage
Example
For the AD8117/AD8118, in an ambient temperature of 85°C,
with all 32 outputs driving 1 V rms into 100 Ω loads and power
supplies at ±2.5 V, follow these steps:
1.
Calculate power dissipation of AD8117/AD8118 using data
sheet quiescent currents. Disregard V
DD
current, as it is
insignificant.
(
VPOS
POS
QUIESCENT
D
I
V
P
,
(
mA
500
V
5
,
QUIESCENT
D
P
) (
+
)
VNEG
NEG
(
5
I
V
×
×
=
)
)
W
5
mA
500
V
=
×
+
×
=
2.
Calculate power dissipation from loads. For a differential
output and ground-referenced load, the output power is
symmetrical in each output phase.
(
OUTPUT
POS
OUTPUT
D
V
V
P
,
,
(
)
(
V
1
V
1
V
5
,
OUTPUT
D
P
)
RMS
OUTPUT
)
Ω
=
RMS
I
,
×
=
mW
15
100
/
×
=
There are 32 output pairs, or 64 output currents.
mW
15
64
,
OUTPUT
D
nP
W
96
.
=
×
=
3.
Subtract the quiescent output stage current for number of
loads (64 in this example). The output stage is either
standing, or driving a load, but the current only needs to
be counted once (valid for output voltages > 0.5 V).
(
)
NEG
POS
OUTPUT
DQ
V
V
P
,
(
V)
5
(
V
5
,
OUTPUT
DQ
P
QUIESCENT
OUTPUT
I
,
×
=
)
mW
25
.
mA
65
.
=
×
=
There are 32 output pairs, or 64 output currents.
25
.
64
,
OUTPUT
DQ
nP
W
53
.
mW
=
×
=
4.
Verify that the power dissipation does not exceed
maximum allowed value.
P
P
,
,
+
=
CHIP
ON
D
P
OUTPUT
DQ
OUTPUT
D
QUIESCENT
D
CHIP
ON
D
nP
nP
,
,
+
=
W
9
W
53
.
W
96
.
W
5
,
=
From Figure 70 or Equation 1, this power dissipation is below
the maximum allowed dissipation for all ambient temperatures
up to and including 85°C.
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