參數(shù)資料
型號(hào)： AD8108
廠商： Analog Devices, Inc.
英文描述： ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75%
中文描述： 325兆赫，8 × 8的緩沖視頻交叉點(diǎn)開(kāi)關(guān)
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 434K
代理商： AD8108
AD8108/AD8109
–15–
REV. 0
T HE ORY OF OPE RAT ION:
T he AD8108 (G = +1) and AD8109 (G = +2) share a common
core architecture consisting of an array of 64 transconductance
(gm) input stages organized as eight 8:1 multiplexers with a
common, 8-line analog input bus. Each multiplexer is basically
a folded-cascode high impedance voltage feedback amplifier
with eight input stages. T he input stages are NPN differential
pairs whose differential current outputs are combined at the
output stage, which contains the high impedance node, com-
pensation and a complementary emitter follower output buffer.
In the AD8108, the output of each multiplexer is fed back di-
rectly to the inverting inputs of its eight gm stages. In the
AD8109, the feedback network is a voltage divider consisting of
a two equal resistors.
T his switched-gm architecture results in a low power crosspoint
switch that is able to directly drive a back terminated video load
(150
) with low distortion (differential gain and differential
phase errors are better than 0.02% and 0.02
°
, respectively).
T his design also achieves high input resistance and low input
capacitance without the signal degradation and power dissipa-
tion of additional input buffers. However, the small input bias
current at any input will increase almost linearly with the num-
ber of outputs programmed to that input.
T he output disable feature of these crosspoints allows larger
switch matrices to be built by simply busing together the out-
puts of multiple 8
×
8 ICs. However, while the disabled output
impedance of the AD8108 is very high (10 M
), that of the
AD8109 is limited by the resistive feedback network (which has
a nominal total resistance of 1 k
that appears in parallel with
the disabled output. If the outputs of multiple AD8109s are
connected through separate back termination resistors, the
loading due to these finite output impedances will lower the
effective back termination impedance of the overall matrix. T his
problem is eliminated if the outputs of multiple AD8109s are
connected directly and share a single back termination resistor
for each output of the overall matrix. T his configuration in-
creases the capacitive loading of the disabled AD8109s on the
output of the enabled AD8109.
APPLIC AT IONS
T he AD8108/AD8109 have two options for changing the pro-
gramming of the crosspoint matrix. In the first, a serial word of
32 bits can be provided that will update the entire matrix each
time. T he second option allows for changing a single output’s
programming via a parallel interface. T he serial option requires
fewer signals, but requires more time (clock cycles) for changing
the programming, while the parallel programming technique re-
quires more signals, but can change a single output at a time and
requires fewer clock cycles to complete programming.
Serial Programming
T he serial programming mode uses the device pins
CE
, CLK ,
DAT A IN,
UPDATE
, and
SER
/PAR. T he first step is to assert
a LOW on
SER
/PAR in order to enable the serial program-
ming mode.
CE
for the chip must be LOW to allow data to be
clocked into the device. T he
CE
signal can be used to address
an individual device when devices are connected in parallel.
T he
UPDATE
signal should be HIGH during the time that data
is shifted into the device’s serial port. Although the data will still
shift in when
UPDATE
is LOW, the transparent, asynchronous
latches will allow the shifting data to reach the matrix. T his will
cause the matrix to try to update to every intermediate state as
defined by the shifting data.
T he data at DAT A IN is clocked in at every down edge of CLK .
A total of 32 data bits must be shifted in to complete the pro-
gramming. For each of the eight outputs, there are three bits
(D0–D2) that determine the source of its input followed by one
bit (D3) that determines the enabled state of the output. If D3
is LOW (output disabled), the three associated bits (D0–D2) do
not matter because no input will be switched to that output.
T he most-significant-output-address data is shifted in first, then
following in sequence until the least-significant-output-address
data is shifted in. At this point
UPDATE
can be taken LOW,
which will cause the programming of the device according to the
data that was just shifted in. T he
UPDATE
registers are asyn-
chronous and when
UPDATE
is LOW, they are transparent.
If more than one AD8108/AD8109 device is to be serially pro-
grammed in a system, the DAT A OUT signal from one device
can be connected to the DAT A IN of the next device to form a
serial chain. All of the CL K ,
CE
,
UPDATE
and
SER
/PAR
pins should be connected in parallel and operated as de-
scribed above. T he serial data is input to the DAT A IN pin of
the first device of the chain, and it will ripple on through to the
last. T herefore, the data for the last device in the chain should
come at the beginning of the programming sequence. T he length
of the programming sequence will be 32 times the number of
devices in the chain.
PARALLE L PROGRAMMING
When using the parallel programming mode, it is not neces-
sary to reprogram the entire device when making changes to
the matrix. In fact, parallel programming allows the modifica-
tion of a single output at a time. Since this takes only one CLK /
UPDATE
cycle, significant time savings can be realized by
using parallel programming.
One important consideration in using parallel programming is
that the
RESET
signal DOES NOT RESET ALL REGIST ERS
in the AD8108/AD8109. When taken low, the
RESET
signal
will only set each output to the disabled state. T his is helpful
during power-up to ensure that two parallel outputs will not be
active at the same time.
After initial power-up, the internal registers in the device will
generally have random data, even though the
RESET
signal was
asserted. If parallel programming is used to program one out-
put, that output will be properly programmed but the rest of the
device will have a random program state depending on the inter-
nal register content at power-up. T herefore, when using parallel
programming, it is essential that ALL OUT PUT S BE PRO-
GRAMMED T O A DESIRED ST AT E AFT ER POWER-UP.
T his will ensure that the programming matrix is always in a
known state. From then on, parallel programming can be used
to modify a single, or more, output at a time.
相關(guān)PDF資料
PDF描述
AD8108-EB ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
AD8108AST 325 MHz, 8 x 8 Buffered Video Crosspoint Switches
AD8109 325 MHz, 8 x 8 Buffered Video Crosspoint Switches
AD8109AST ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
AD8109* 325 MHz. 8 3 8 Buffered Video Crosspoint Switches
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD8108_05 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:325 MHz, 8 ?? 8 Buffered Video Crosspoint Switches
AD8108AST 制造商:Analog Devices 功能描述:Analog Video Crosspoint 325MHz 8 x 8 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:TQFP 250MHZ 8X8 G=+1 BUF VID XPOINT SW. - Tape and Reel 制造商:Analog Devices 功能描述:SWITCH CROSSPOINT 8X8 SMD 8108
AD8108ASTZ 功能描述:IC VIDEO CROSSPOINT SWIT 80LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開(kāi)關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR)
AD8108ASTZ 制造商:Analog Devices 功能描述:IC SWITCH VIDEO
AD8108ASTZ2 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:325 MHz, 8 ?? 8 Buffered Video Crosspoint Switches
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