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參數(shù)資料
| 型號(hào)： | AD8048ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VF GP LDIST 50MA 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 1000 V/µs |
| -3db帶寬： | 260MHz |
| 電流 - 輸入偏壓： | 1µA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 5.9mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 6 V ~ 12 V，±3 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
REV. A
–14–
AD8047/AD8048
Choose
FO = Cutoff Frequency = 20 MHz
= Damping Ratio = 1/Q = 2
H = Absolute Value of Circuit Gain =
–R4
R1
= 1
Then,
k
= 2 π F
O C1
C2
=
4 C1(H
+1)
α2
R1
= α
2 HK
R3
=
α
2 K (H
+1)
R4
= H(R1)
A/D Converter Driver
As A/D converters move toward higher speeds with higher reso-
lutions, there becomes a need for high performance drivers that
will not degrade the analog signal to the converter. It is desir-
able from a system’s standpoint that the A/D be the element in
the signal chain that ultimately limits overall distortion. This
places new demands on the amplifiers used to drive fast, high
resolution A/Ds.
With high bandwidth, low distortion, and fast settling time,
the AD8047 and AD8048 make high performance A/D drivers
for advanced converters. Figure 12 is an example of an AD8047
used as an input driver for an AD872A, a 12-bit, 10 MSPS
A/D converter.
MSB
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
AVDD
AGND
VINA
REF GND
REF IN
REF OUT
AVSS
AGND
OTR
CLK
DRGND
DRVDD
DGND
DVDD
19
18
17
16
15
14
13
12
11
10
9
8
24
25
3
26
28
27
1
20
21
23
22
6
7
4
5
VINB
–5V ANALOG
AD872A
+5V ANALOG
ANALOG IN
DIGITAL OUTPUT
0.1 F
1 F
10
49.9
CLOCK INPUT
+5V ANALOG
+5V DIGITAL
2
–5V
ANALOG
10 F
0.1 F
AD8047
3
2
7
6
4
Figure 12. AD8047 Used as Driver for an AD872A, a 12-Bit, 10 MSPS A/D Converter
Layout Considerations
The specified high speed performance of the AD8047 and
AD8048 requires careful attention to board layout and compo-
nent selection. Proper RF design techniques and low-pass
parasitic component selection are mandatory.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low
impedance path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for the supply bypassing (see
Figure 12). One end should be connected to the ground plane
and the other within 1/8 inch of each power pin. An additional
large (0.47
F to 10 F) tantalum electrolytic capacitor should
be connected in parallel, though not necessarily so close, to the
supply current for fast, large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the inverting
input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50
or 75 and be properly termi-
nated at each end.
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