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參數(shù)資料
| 型號： | AD802 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Clock Recovery and Data Retiming Phase-Locked Loop(時(shí)鐘恢復(fù)和重定時(shí)PLL) |
| 中文描述： | 時(shí)鐘恢復(fù)和數(shù)據(jù)重定時(shí)鎖相環(huán)（時(shí)鐘恢復(fù)和重定時(shí)鎖相環(huán)） |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 258K |
| 代理商： | AD802 |
AD800/AD802
REV. B
–12–
OUT LINE DIME NSIONS
Dimensions shown in inches and (mm).
20-Pin Small Outline IC Package (R-20)
1
10
11
20
0.50 (1.27)
BSC
0.015 (0.38)
0.007 (0.18)
0.019 (0.48)
0.014 (0.36)
0.011 (0.28)
0.004 (0.10)
0.050 (1.27)
0.016 (0.40)
0.104 (2.64)
0.093 (2.36)
0.419 (10.65)
0.394 (10.00)
0.300 (7.60)
0.292 (7.40)
0.512 (13.00)
0.496 (12.60)
20-Pin Cerdip Package (Q-20)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15
°
0
°
0.005 (0.13) MIN
PIN 1
0.098 (2.49) MAX
0.310 (7.87)
0.220 (5.59)
10
11
1
20
1.060 (26.92) MAX
0.200
(5.08)
MAX
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
PLANE
C
P
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