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| 型號： | AD8011ANZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP CF LP LDIST 30MA 8DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 放大器類型： | 電流反饋 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 3500 V/µs |
| -3db帶寬： | 400MHz |
| 電流 - 輸入偏壓： | 5µA |
| 電壓 - 輸入偏移： | 2000µV |
| 電流 - 電源： | 1.3mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 769 (CN2011-ZH PDF) |
REV. C
AD8011
–11–
1E+03
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
FREQUENCY (Hz)
140
120
100
80
60
20
0
40
GAIN
(dB
)
0
PHASE
(Degrees)
–40
–80
–120
–160
–200
–240
–280
PHASE
GAIN
TO(s)
Figure 9. Open-Loop Transimpedance Gain
Note that the ac open-loop plots in Figures 8, 9, and 10 are based
on the full SPICE AD8011 simulations and do not include
external parasitics (see equations below). Nevertheless, these ac
loop equations still provide a good approximation to simulated
and actual performance up to the CLBW of the amplifier. Typi-
cally, gmc
R1 is –4, resulting in AO(s) having a right half plane
pole. In the time domain (inverse Laplace of AO), it appears as
unstable, causing VO to exponentially rail out of its linear region.
When the loop is closed however, the BW is greatly extended and
the transimpedance gain, TO (s), overrides and directly controls
the amplifiers stability behavior due to ZI approaching 1/2 gmf
for s>>1/
τ1 (see Figure 10). This can be seen by the Z
I (s) and
AV (s) noninverting transfer equations below.
Zs
g
mc
R
S
g
mc
R
g
mf
S
I ()
( –
)
–
()
=
×
+
×+
11
1
11
1
21 1
τ
As
G
A
R
T
S
G
g
mf
T
R
T
V
O
F
OO
F
O
()
=
++
+
+
11
2
1
τ
1E+03
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
400
370
340
310
280
220
190
FREQUENCY (Hz)
250
RESISTANCE
(
)
20
PHASE
(Degrees)
0
–20
–40
–120
160
130
100
–140
–160
–180
–60
–80
–100
SERIES 1
IMPEDANCE
ZI(s)
SERIES 2
PHASE
Figure 10. Open-Loop Inverting Input Impedance
ZI (s) goes positive real and approaches 1/2 gmf as
approaches
(gmc R1 – 1)/
τ1. This results in the input resistance for the A
V (s)
complex term being 1/2 gmf, the parallel thermal emitter
resistances of Q3/Q4. Using the computed CLBW from AV (s)
and the nominal design values for the other parameters, results in
a closed-loop 3 dB BW equal to the open-loop corner frequency
(1/2
πτ1) × 1/[G/(2 gmf
TO) + RF/TO]. For a fixed RF, the
3 dB BW is controlled by the RF/TO term for low gains and
G/(2 gmf
TO) for high gains. For example, using nominal design
parameters and R1 = 1 k
(which results in a nominal TO of
1.2 M
), the computed BW is 80 MHz for G = 0 (inverting
I-V mode with RN removed) and 40 MHz for G = +10/–9.
DRIVING CAPACITIVE LOADS
The AD8011 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, the best
settling response is obtained by the addition of a small series
resistance as shown in Figure 11. The accompanying graph shows
the optimum value for RSERIES versus capacitive load. It is worth
noting that the frequency response of the circuit when driving
large capacitive loads will be dominated by the passive roll-off
of RSERIES and CL.
1k
RL
1k
CL
RSERIES
1k
AD8011
Figure 11. Driving Capacitive Load
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