參數(shù)資料
型號(hào)： AD8002
廠商： Analog Devices, Inc.
英文描述： Dual 600 MHz, 50 mW Current Feedback Amplifier(600MHz,50mW雙電流反饋放大器)
中文描述： 雙600兆赫，50毫瓦電流反饋放大器（頻率600MHz，50mW的雙電流反饋放大器）
文件頁(yè)數(shù)： 14/16頁(yè)
文件大?。?/td> 507K
代理商： AD8002
AD8002
REV. B
–14–
T able I. Recommended Component Values
AD8002AN (DIP)
Gain
–1
+1
AD8002AR (SOIC)
Gain
–1
+1
Component
–10
–2
+2
+10
+100 –10
–2
+2
+10
+100
R
F
(
)
R
G
(
)
R
BT
(Nominal) (
)
R
C
(
)*
R
S
(
)
R
T
(Nominal) (
)
Small Signal BW (MHz)
0.1 dB Flatness (MHz)
499
49.9
49.9
549
274
49.9
576
576
49.9
1210
–
49.9
75
750
750
49.9
75
499
54.9
49.9
0
1000 499
10
49.9
0
499
249
49.9
549
549
49.9
953
–
49.9
75
681
681
49.9
75
499
54.9
49.9
0
1000
10
49.9
0
49.9
49.9
50
–
270
45
50
61.9
380
80
50
54.9
410
130
50
–
250
50
50
61.9
410
100
50
54.9
410
100
49.9
600
35
49.9
500
60
49.9
170
24
49.9
17
3
49.9
600
35
49.9
500
90
49.9
170
24
49.9
17
3
*R
C
is recommended to reduce peaking and minimizes input reflections at frequencies above 300 MHz. However, R
C
is not required.
Layout Considerations
T he specified high speed performance of the AD8002 requires
careful attention to board layout and component selection.
Proper R
F
design techniques and low parasitic component selec-
tion are mandatory.
T he PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance ground path. T he ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Figure
49). One end should be connected to the ground plane and the
other within 1/8 in. of each power pin. An additional large
(4.7
μ
F–10
μ
F) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.
T he feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). T hese should be designed with a
characteristic impedance of 50
or 75
and be properly termi-
nated at each end.
Inverting Configuration
Supply Bypassing
Noninverting Configuration
R
F
R
BT
IN
+V
S
–V
S
R
S
R
T
R
G
OUT
C1
0.1
μ
F
C3
10
μ
F
C2
0.1
μ
F
C4
10
μ
F
+V
S
–V
S
R
F
R
BT
IN
+V
S
–V
S
R
T
R
G
OUT
*R
C
*SEE TABLE I
Figure 49. Inverting and Noninverting Configurations
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