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參數(shù)資料
| 型號： | AD7992BRMZ-1REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 2CHAN I2C 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 79k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.2mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
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AD7992
Rev. 0 | Page 26 of 28
MODE 2 – COMMAND MODE
Mode 2 allows a conversion to be automatically initiated any
time a write operation occurs. In order to use this mode,
Command Bits C2 to C1 in the address pointer byte, shown in
Table 7, must be programmed. Command Bits C4 and C3 are
not used and should contain zeros at all times.
To select a channel for conversion in Mode 2, set the corres-
ponding channel command bit in the address pointer byte
(see Table 24). To select both analog input channels for con-
version, set both C1 and C2 to 1. When all four command
bits are 0, this mode is not used.
Figure 28 illustrates a 2-byte read operation from the conver-
sion result register. Prior to the read operation, ensure that the
address pointer is pointing to the conversion result register.
When the contents of the address pointer register are being
loaded, if Command Bits C2 or C1 are set, the AD7992 begins
to power up and convert upon the selected channel(s). Power-
up begins on the fifth SCL falling edge of the address point byte
(see point A in Figure 32). Table 24 shows the channel selection
in this mode via Command Bits C1 and C2 in the address
pointer register. The wake-up and conversion time together
should take approximately 3 s, and the conversion begins
when the last Command Bit, C1, has been clocked in midway
through the write to the address pointer register. Following
this, the AD7992 must be addressed again to tell it that a read
operation is required. The read then takes place from the
conversion result register. This read accesses the result from
the conversion selected via the command bits. If Command Bits
C2, C1 are set to 1,1, a 4-byte read is necessary. The first read
accesses the data from the conversion on VIN1. While this read
takes place, a conversion occurs on VIN2. The second read
operates.
After the conversion result has been read, and if further read
bytes are issued, the ADC continuously converts on the selected
input channel(s). This has the effect of increasing the overall
throughput rate of the ADC.
When operating the AD7992-1 in Mode 2 with high speed
mode, 3.4 MHz SCL, the conversion may not be complete
before the master tries to read the conversion result. In this
case, the AD7992-1 holds the SCL line low during the ACK
clock after the read address until the conversion is complete.
When the conversion is complete, the AD7992-1 releases the
SCL line and the master can then read the conversion result.
After a conversion is initiated in this mode by setting the
command bits in the address pointer byte, if the AD7992
receives a STOP or NACK from the master, the AD7992 stops
converting.
Table 24. Address Pointer Byte—Command Bits
C2
C1
Analog Input Channel
0
No conversion
0
1
Conversion on VIN1
1
0
Conversion on VIN2
1
Conversion on VIN1 followed by conversion on VIN2
9
11
A
9
S
WA
A
Sr
RA
A
SECOND DATA BYTE
(LSBs)
FIRST DATA BYTE
(MSBs)
COMMAND/ADDRESS
POINT BYTE
7-BIT ADDRESS
A
SDA
11
9
SCL
SDA
SCL
9
Sr/P
8
ACK BY
AD7992
ACK BY
AD7992
ACK BY
MASTER
NACK BY
MASTER
ACK BY
AD7992
03263-0-012
Figure 32. Mode 2 Operation
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