參數(shù)資料
型號(hào): AD7992BRMZ-1REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 17/29頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 2CHAN I2C 10MSOP
標(biāo)準(zhǔn)包裝: 3,000
位數(shù): 12
采樣率(每秒): 79k
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 2.2mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極
AD7992
Rev. 0 | Page 23 of 28
READING DATA FROM THE AD7992
Reading data from the AD7992 is a 1- or 2-byte operation.
Reading back the contents of the alert status register, the config-
uration register, or the cycle timer register is a single-byte read
operation, as shown in Figure 28. This assumes the particular
register address has previously been set up by a single-byte write
operation to the address pointer register (see Figure 25). Once
the register address has been set up, any number of reads can
be performed from that particular register without having to
write to the address pointer register again. If a read from a
different register is required, the relevant register address has
to be written to the address pointer register, and again any
number of reads from this register may then be performed.
Reading data from the conversion result register, DATAHIGH
registers, DATALOW registers, or hysteresis registers is a 2-byte
operation, as shown in Figure 29. The same rules apply for a
2-byte read as a 1-byte read.
When reading data back from a register, such as the conversion
result register, if more than two read bytes are supplied, the
same or new data is read from the AD7992 without the need to
re-address the device. This allows the master to continuously
read from a data register without having to re-address the
AD7992.
SDA
11
99
D7
D6
D5
D2
D1
D0
R/W
A0
A1
A2
A3
0
1
SCL
D4
D3
0
03263-0-009
START BY
MASTER
ACK. BY
AD7992
NO ACK. BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
SINGLE DATA BYTE FROM AD7992
Figure 28. Reading a Single Byte of Data from a Selected Register
SDA
11
9
ALERT-
FLAG
ZERO
D10
D9
D8
A0
A1
A2
A3
0
SCL
1
D11
1
D7
D6
D5
D2
D1/0
D0/0
D4
D3
SCL (CONTINUED)
SDA (CONTINUED)
ZERO CHID
R/W
03263-0-010
9
START BY
MASTER
ACK. BY
AD7992
NO ACK. BY
MASTER
ACK. BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM
AD7992
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM
AD7992
Figure 29. Reading Two Bytes of Data from the Conversion Result Register
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