
AD7951
Data Sheet
Rev. A | Page 26 of 32
BUSY
SYNC
SDCLK
SDOUT
12
3
12
13
14
D13
D12
D2
D1
D0
X
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
CNVST
CS, RD
EXT/INT = 0
t23
t22
t16
t15
t14
t29
t19
t21
t20
t18
t28
t30
t24
t25
t26
t27
t3
06
39
6-
03
9
Figure 39. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
D13
D12
D2
D1
D0
X
12
3
12
13
14
BUSY
SYNC
SDCLK
SDOUT
CNVST
CS, RD
t23
t18
t15
t14
t17
t3
t22
t16
t1
t25
t26
t24
t27
t19
t20 t21
06
39
6-
04
0
Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)