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參數(shù)資料
| 型號： | AD7948BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT MULTIPLYING 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 設(shè)置時間： | 600ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 25µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 1.7M |
AD7943/AD7945/AD7948
REV. B
–4–
AC PERFORMANCE CHARACTERISTICS
NORMAL MODE
Parameter
B Grades
T Grade
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
600
700
ns typ
To 0.01% of Full-Scale Range. VREF =
+10 V; DAC Latch Alternately Loaded with
All 0s and All 1s
Digital to Analog Glitch Impulse
60
nV-s typ
Measured with VREF = 0 V. DAC Latch
Alternately Loaded with All 0s and All 1s
Multiplying Feedthrough Error
–75
dB max
DAC Latch Loaded with All 0s
Output Capacitance
60
pF max
All 1s Loaded to DAC
30
pF max
All 0s Loaded to DAC
Digital Feedthrough (AD7943)
5
nV-s typ
Feedthrough to the DAC Output with
LD1,
LD2 High and Alternate Loading of All 0s
and All 1s into the Input Shift Register
Digital Feedthrough (AD7945, AD7948) 5
5
nV-s typ
Feedthrough to the DAC Output with
CS
High and Alternate Loading of All 0s and
All 1s to the DAC Bus
Total Harmonic Distortion
–83
Output Noise Spectral Density
@ 1 kHz
35
nV/
√Hz typ All 1s Loaded to DAC. V
REF = 0 V. Output
Op Amp Is OP07
Specifications subject to change without notice.
(AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V. AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 =AGND =
0 V. VREF = 6 V rms, 1 kHz sine wave; TA = TMIN to TMAX; DAC output op amp is AD843; unless otherwise noted.) These characteristics are in-
cluded for Design Guidance and are not subject to test.
AC PERFORMANCE CHARACTERISTICS
BIASED MODE (AD7943: VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 1.23 V. AD7945, AD7948: VDD = +3 V to +5.5 V; VIOUT1 = AGND =
1.23 V. VREF = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; TA = TMIN to TMAX; unless otherwise noted.) These
characteristics are included for Design Guidance and are not subject to test.
Parameter
A Grades
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
5
s typ
To 0.01% of Full-Scale Range. VREF = 0 V
DAC Latch Alternately Loaded with All 0s and All 1s
Digital to Analog Glitch Impulse
60
nV-s typ
VREF = 1.23 V. DAC Register Alternately Loaded
with All 0s and All 1s
Multiplying Feedthrough Error
–75
dB max
DAC Latch Loaded with All 0s
Output Capacitance
60
pF max
All 1s Loaded to DAC
30
pF max
All 0s Loaded to DAC
Digital Feedthrough
5
nV-s typ
Feedthrough to the DAC Output with
LD1, LD2
High and Alternate Loading of All 0s and All 1s
into the Input Shift Register
Digital Feedthrough (AD7945, AD7948)
5
nV-s typ
Feedthrough to the DAC Output with CS High
and Alternate Loading of All 0s and All 1s to the
DAC Bus
Total Harmonic Distortion
–83
dB typ
Output Noise Spectral Density
@ 1 kHz
25
nV/
√Hz typ
All 1s Loaded to DAC. VREF = 1.23 V
Specifications subject to change without notice.
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