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參數(shù)資料
| 型號： | AD7945BRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT MULT PARALL 20SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 600ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 25µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 1.7M |
AD7943/AD7945/AD7948
REV. B
–5–
(TA = TMIN to TMAX, unless otherwise noted)
Limit @
Parameter
VDD = +3 V to +3.6 V
VDD = +4.5 V to +5.5 V
Units
Description
tSTB
2
60
40
ns min
STB Pulsewidth
tDS
15
10
ns min
Data Setup Time
tDH
35
25
ns min
Data Hold Time
tSRI
55
35
ns min
SRI Data Pulsewidth
tLD
55
35
ns min
Load Pulsewidth
tCLR
55
35
ns min
CLR Pulsewidth
tASB
0
ns min
Min Time Between Strobing Input Shift
Register and Loading DAC Register
tSV
3
60
35
ns max
STB Clocking Edge to SRO Data Valid Delay
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1
s on any digital input.
2STB mark/space ratio range is 60/40 to 40/60.
3t
SV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
tSTB
STB1,
STB2,
STB4
STB3
tDS
tDH
tSRI
SRI
DB11(N)
(MSB)
DB10(N)
DB0(N)
DB0(N–1)
DB10(N–1)
LD1,
LD2,
CLR
SRO
tSV
tLD, tCLR
tASB
Figure 1. AD7943 Timing Diagram
TO OUTPUT
PIN
CL
50pF
1.6mA
IOL
+2.1V
IOH
200 A
Figure 2. Load Circuit for Digital Output Timing Specifications
AD7943 TIMING SPECIFICATIONS1
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