Sample tested at initial release to ensure compliance. All input signals are spec" />
參數(shù)資料
型號(hào)： AD7940-DBRD
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7940 STAMP SPI
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ Vdd
在以下條件下的電源（標(biāo)準(zhǔn)）： 17mW @ 100kSPS & 5V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7940
已供物品： 板
相關(guān)產(chǎn)品： AD7940BRJZ-REEL7DKR-ND - IC ADC 14BIT 100KSPS SOT-23-6
AD7940BRJZ-REEL7CT-ND - IC ADC 14BIT 100KSPS SOT-23-6
AD7940BRJZ-REEL7TR-ND - IC ADC 14BIT 100KSPS SOT-23-6
AD7940BRM-ND - IC ADC 14BIT UNIPOLAR 8-MSOP
AD7940BRM-REEL7TR-ND - IC ADC 14BIT UNIPOLAR 8-MSOP
AD7940
Rev. A | Page 5 of 20
TIMING SPECIFICATIONS
Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from
a voltage level of 1.6 V.
VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at T
MIN, TMAX
Parameter
3 V
5 V
Unit
Description
f
SCLK
250
kHz min
2.5
MHz max
t
CONVERT
16 × t
SCLK
16 × t
SCLK
min
t
QUIET
50
ns min
Minimum quiet time required between bus relinquish and start of
next conversion
t
1
10
ns min
Minimum CS pulse width
t
2
10
ns min
CS to SCLK setup time
t
3
48
35
ns max
Delay from CS until SDATA three-state disabled
t
4
2
120
80
ns max
Data access time after SCLK falling edge
t
5
0.4 t
SCLK
0.4 t
SCLK
ns min
SCLK low pulse width
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min
SCLK high pulse width
t
7
10
ns min
SCLK to data valid hold time
t
8
45
35
ns max
SCLK falling edge to SDATA high impedance
t
POWER-UP
1
s typ
Power up time from full power-down
1 Mark/space ratio for the SCLK input is 40/60 to 60/40.
2 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
3 t
8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
03305-0-002
200
A
IOL
200
A
IOH
1.6V
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output Timing Specification
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