參數(shù)資料
型號(hào)： AD7938BSUZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/36頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 8CHAN 32TQFP
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 12
采樣率（每秒）： 1.5M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 13.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；4 個(gè)差分，單極；4 個(gè)偽差分，單極；7 偽差分，單極
配用： EVAL-AD7938CBZ-ND - EVAL BOARD FOR AD7938
Data Sheet
AD7938/AD7939
Rev. C | Page 29 of 36
POWER vs. THROUGHPUT RATE
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7938/AD7939 are only powered
up for the duration of the conversion. Therefore, the average
power consumption per cycle is significantly reduced. Figure 41
shows a plot of the power vs. throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V. For example, if
the maximum CLKIN frequency of 25.5 MHz is used to
minimize the conversion time, this accounts for only 0.525 s of
the overall cycle time while the AD7938/AD7939 remains in
standby mode for the remainder of the cycle. If the devices run
at a throughput rate of 10 kSPS, for example, the overall cycle
time is 100 s.
Figure 42 shows a plot of the power vs. throughput rate when
operating in normal mode for both VDD = 5 V and VDD = 3 V. In
both plots, the figures apply when using the internal reference.
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7938/AD7939 remain in standby for a
greater time in every cycle. Additionally, the current consumption,
when converting, should be lower than the specified maximum
of 2.7 mA with VDD = 5 V, or 2.0 mA with VDD = 3 V.
THROUGHPUT (kSPS)
PO
W
ER
(m
W
)
1.8
0.8
1.0
1.2
1.4
1.6
0
0.6
0.4
0.2
0
20
40
60
80
100
120
140
03715-
042
TA = 25°C
VDD = 5V
VDD = 3V
Figure 41. Power vs. Throughput in
Autostandby Mode Using Internal Reference
THROUGHPUT (kSPS)
PO
W
ER
(m
W
)
10
4
5
6
7
8
9
0
3
2
1
0
200
400
600
800
1000
1200
1600
1400
03715-
043
TA = 25°C
VDD = 5V
VDD = 3V
Figure 42. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7938/AD7939 to ADSP-21xx Interface
Figure 43 shows the AD7938/AD7939 interfaced to the ADSP-
21xx series of DSPs as a memory-mapped device. A single wait
state may be necessary to interface the AD7938/AD7939 to the
ADSP-21xx depending on the clock speed of the DSP. The wait
state can be programmed via the data memory wait state
control register of the ADSP-21xx (see the ADSP-21xx family
User’s Manual for details). The following instruction reads from
the AD7938/AD7939:
MR = DM (ADC)
where ADC is the address of the AD7938/AD7939.
AD7938/
AD7939*
ADSP-21xx*
WR
RD
DB0 TO DB11
D0 TO D23
A0 TO A15
DMS
IRQ2
BUSY
CS
CONVST
DSP/USER SYSTEM
WR
RD
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
03715-
045
Figure 43. Interfacing to the ADSP-21xx
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