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參數(shù)資料
| 型號： | AD7884BQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SAMPLING HS 40-CDIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 166k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 325mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-Cerdip |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
REV. E
AD7884/AD7885
–12–
Dynamic Performance
With a combined conversion and acquisition time of 6
s, the
AD7884/AD7885 is ideal for wide bandwidth signal processing appli-
cations. Signal-to-(noise + distortion), total harmonic distortion,
peak harmonic or spurious noise, and intermodulation distortion
are all specified. Figure 16 shows a typical FFT plot of a 1.8 kHz,
±5 V input after being digitized by the AD7884/AD7885.
0
–150
–60
–120
–90
–30
2048 POINT FFT
dB
fIN = 1.8kHz, 5V SINE WAVE
fSAMPLE = 163kHz
SNR = 87dB
THD = –95dB
Figure 16. AD7884/AD7885 FFT Plot
Effective Number of Bits
The formula for SNR (see Terminology section) is related to
the resolution or number of bits in the converter. Rewriting the
formula, below, gives a measure of performance expressed in
effective number of bits (N).
N
SNR
=
()
176 6 02
..
16
10
80
13
11
20
12
0
15
14
60
40
FREQUENCY – kHz
EFFECTIVE
NUMBER
OF
BITS
Figure 17. Effective Number of Bits vs. Frequency
The effective number of bits for a device can be calculated from
its measured SNR. Figure 17 shows a typical plot of effective
number of bits versus frequency for the AD7884. The sampling
frequency is 166 kHz.
MICROPROCESSOR INTERFACING
The AD7884/AD7885 is designed on a high speed process
that results in very fast interfacing timing (data access time of
57 ns max). The AD7884 has a full 16-bit parallel bus, and the
AD7885 has an 8-bit wide bus. The AD7884, with its parallel
interface, is suited to 16-bit parallel machines whereas the
AD7885, with its byte interface, is suited to 8-bit machines.
Some examples of typical interface configurations follow.
AD7884 to MC68000 Interface
Figure 18 shows a general interface diagram for the MC68000
16-bit microprocessor to the AD7884. In Figure 18, conversion
is initiated by bringing
CSA low (i.e., writing to the appropriate
address). This allows the processor to maintain control over the
complete conversion process. In some cases, it may be more
desirable to control conversion independent from the processor.
This can be done by using an external sampling timer.
MC68000
AD7884
ADDRESS
DECODE LOGIC
CONVST
CS
RD
DB15–DB0
R/
W
DATA BUS
ADDRESS BUS
A23–A1
D15–D0
DTACK
AS
CSA
CSB
Figure 18. AD7884 to MC68000 Interface
Once conversion has been started, the processor must wait until
it is completed before reading the result. There are two ways of
ensuring this. The first way is to simply use a software delay to
wait for 6.5
s before bringing CS and RD low to read the data.
The second way is to use the
BUSY output of the AD7884 to
generate an interrupt in the MC68000. Because of the nature of
its interrupts, the MC68000 requires additional logic (not shown
in Figure 18) to allow it to be interrupted correctly. For full
information on this, consult the MC68000 User’s Manual.
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