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參數(shù)資料
| 型號： | AD7884BQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SAMPLING HS 40-CDIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 166k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 325mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-Cerdip |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
REV. E
AD7884/AD7885
–8–
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal (AGND).
Positive Gain Error
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (+VREF+S – 1 LSB) after bipolar zero
error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF+S + 1 LSB) after bipolar zero
error has been adjusted out.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by
Signal to Noise
Distortion
N
dB
+
() =+
()
602
1 76
..
Thus for an ideal 16-bit converter, this is 98 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7884/AD7885, it is
defined as
THD dB
VVV
V
()
log
=
++
+
20
2
3
2
4
2
5
2
6
2
1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to fS/2 and excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the larg-
est harmonic in the spectrum, but for parts where the harmonics
are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa
± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
The AD7884/AD7885 is tested using the CCIFF standard where
two input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the THD
specification, where it is the ratio of the rms sum of the individual
distortion products to the rms amplitude of the fundamental
expressed in dB.
Power Supply Rejection Ratio
This is the ratio of the change in positive gain error to the change
in VDD or VSS, in dB. It is a dc measurement.
OPERATIONAL DIAGRAM
An operational diagram for the AD7884/AD7885 is shown in
Figure 6. It is set up for an analog input range of
±5 V. If a ±3 V
input range is required, A1 should drive
±3V
INS and
±3V
INF
with
±5VINS, ±5VINF being tied to system AGND.
3VINF
5VINF
–5V
+5V
AD711, AD845,
OR AD817
AD817
AGNDS
AGNDF
AD7884/
AD7885
AD845, AD817,
OR EQUIVALENT
NOTE: POWER SUPPLY DECOUPLING NOT SHOWN
GND
DGND
VDD = +5V
CONTROL
INPUTS
VINV
VREF+S
VREF+F
VREF–
3VINS
5VINS
AVSS
VDD
AVDD
VSS
VIN
AD780
2
6
8
4
10 F
A1
A2
A3
A4
DATA
OUTPUTS
AD845, AD817,
OR EQUIVALENT
Figure 6. AD7884/AD7885 Operational Diagram
The chosen input buffer amplifier (A1) should have low noise and
distortion and fast settling time for high bandwidth applications.
The AD711, AD845, and AD817 are suitable op amps.
A2 is the force, sense amplifier for AGND. The AGNDS pin
should be at zero potential. Therefore, the amplifier must have a
low input offset voltage and good noise performance. It must
also have the ability to deal with fast current transients on the
AGNDS pin. The AD817 has the required performance and is
the recommended amplifier.
If AGNDS and AGNDF are simply tied together to star
ground instead of buffering, the SNR and THD are not signifi-
cantly degraded. However, dc specifications like INL, bipolar
zero, and gain error will be degraded.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD7885AAP | 制造商:Analog Devices 功能描述:16-Bit, High Speed Sampling ADCs |
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