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參數(shù)資料
| 型號(hào)： | AD7884BPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SAMPLING HS 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 166k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 325mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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REV. D
–3–
AD7884/AD7885
TIMING CHARACTERISTICS1
Limit at 25 C
Limit at TMIN, TMAX
Parameter
(All Versions)
(A, B, and J Versions) Unit
Conditions/Comments
t1
50
ns min
CONVST Pulsewidth
t2
100
ns max
CONVST to BUSY Low Delay
t3
00
ns min
CS to RD Setup Time
t4
60
ns min
RD Pulsewidth
t5
00
ns min
CS to RD Hold Time
t6
2
57
ns max
Data Access Time after
RD
t7
3
55
ns min
Bus Relinquish Time after
RD
50
ns max
t8
40
ns min
New Data Valid before Rising Edge of
BUSY
t9
10
80
ns min
HBEN to
RD Setup Time
t10
25
ns min
HBEN to
RD Hold Time
t11
60
ns min
HBEN Low Pulse Duration
t12
60
ns min
HBEN High Pulse Duration
t13
55
70
ns max
Propagation Delay from HBEN Falling to Data Valid
t14
55
70
ns max
Propagation Delay from HBEN Rising to Data Valid
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t
6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t
7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics
is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V
5%, VSS = –5 V
5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5.)
TO OUTPUT PIN
2.1V
CL
100pF
200 A
IOH
1.6mA
IOL
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
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