參數(shù)資料
型號(hào)： AD7884BPZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/16頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT SAMPLING HS 44-PLCC
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 16
采樣率（每秒）： 166k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 325mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
a
AD7884/AD7885
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
2003 Analog Devices, Inc. All rights reserved.
REV. E
LC2MOS
16-Bit, High Speed Sampling ADCs
3VINF
AD7884
TIMER
CONTROL
DGND
CS
RD
BUSY
DB15
AGNDS AGNDF AVDD
GND
DB0
CONVST
VDD
9
16
VREF–
R3
3k
C1
SW1
SW2
9-BIT
ADC
LATCH
+
ALU
O
U
T
P
U
T
D
R
I
V
E
R
S
16-BIT
ACCURATE
DAC
R2
3k
3VINS
R1
5k
R5
4k
A2
SW3
R6
2k
R7
2k
R8
2k
5VINF
5VINS
AVSS
VSS
VREF+FVREF+SVINV
VREF–
R4
4k
A1
AD7885
TIMER
CONTROL
DGND
CS
RD
BUSY
DB7
AGNDS AGNDF AVDD
GND
DB0
CONVST
VDD
9
16
8
VREF–
R3
3k
C1
SW1
SW2
9-BIT
ADC
LATCH
+
ALU
O
U
T
P
U
T
D
R
I
V
E
R
S
16-BIT
ACCURATE
DAC
R2
3k
3VIN
R1
5k
R5
4k
A2
SW3
R6
2k
R7
2k
R8
2k
5VINF
5VINS
AVSS
VSS
VREF+FVREF+SVINV
VREF–
R4
4k
HBEN
A1
FEATURES
Monolithic Construction
Fast Conversion: 5.3
s
High Throughput Rate: 166 kSPS
Low Power: 250 mW
APPLICATIONS
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics
GENERAL DESCRIPTION
The AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3
s. The maximum throughput rate is 166 kSPS. It uses a
two-pass flash architecture to achieve this speed. Two input
ranges are available:
±5 V and ±3 V. Conversion is initiated by
the
CONVST signal. The result can be read into a microprocessor
using the
CS and RD inputs on the device. The AD7884 has a
16-bit parallel reading structure while the AD7885 has a byte reading
structure. The conversion result is in twos complement code.
The AD7884/AD7885 has its own internal oscillator that controls
conversion. It runs from
±5 V supplies and needs a V
REF+ of 3 V.
The AD7884 is available in a 40-lead CERDIP package and a
44-lead PLCC package.
The AD7885 is available in a 28-lead CERDIP package and the
AD7885A is available in a 44-lead PLCC package.
FUNCTIONAL BLOCK DIAGRAMS
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