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參數(shù)資料
| 型號： | AD7874SQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 4CH 5V 28-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 116k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 電壓電源： | 雙 ± |
| 電源電壓： | ±5V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-CDIP |
| 包裝： | 管件 |
AD7874
REV. C
–3–
TIMING CHARACTERISTICS1
Parameter
A, B Versions
S Version
Units
Conditions/Comments
t1
50
ns min
CONVST
Pulse Width
t2
0
ns min
CS
to RD Setup Time
t3
60
70
ns min
RD
Pulse Width
t4
0
ns min
CS
to RD Hold Time
t5
60
ns max
RD
to INT Delay
t6
2
57
70
ns max
Data Access Time after RD
t7
3
55
ns min
Bus Relinquish Time after RD
45
50
ns max
t8
130
150
ns min
Delay Time between Reads
tCONV
31
s min
CONVST
to INT, External Clock
32.5
s max
CONVST
to INT, External Clock
31
s min
CONVST
to INT, Internal Clock
35
s max
CONVST
to INT, Internal Clock
tCLK
10
s max
Minimum Input Clock Period
NOTES
1Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25
°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2t
6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t
7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V
5%, VSS = –5 V
5%, AGND = DGND = O V, tCLK = 2.5 MHz external unless
otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40
°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55
°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300
°C
Power Dissipation (Any Package) to +75
°C . . . . . . 1,000 mW
Derates above +75
°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
TO OUTPUT
PIN
1.6mA
2.1V
+
200
A
50pF
Figure 1. Load Circuit for Access Time
TO OUTPUT
PIN
1.6mA
2.1V
+
200
A
50pF
Figure 2. Load Circuit for Bus Relinquish Time
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7874 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
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