(VDD = +5 V 5%, V<" />
參數(shù)資料
型號： AD7869JRZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/16頁
文件大?。?/td> 0K
描述： IC I/O PORT 14BIT ANLG 28SOIC
標準包裝： 1
應(yīng)用： 模擬 I/O
接口： TTL/CMOS
電源電壓： 4.75 V ~ 5.25 V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
安裝類型： 表面貼裝
–2–
AD7869–SPECIFICATIONS
ADC SECTION
(VDD = +5 V
5%, VSS = –5 V
5%, AGND = DGND = 0 V, fCLK = 2.0 MHz external.
All specifications TMIN to TMAX unless otherwise noted.)
Parameter
J Version
1
A Version
1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio
3, 4 (SNR) @ +25
°C
78
dB min
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
TMIN to TMAX
78
77
dB min
Total Harmonic Distortion (THD)
–86
dB typ
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
Peak Harmonic or Spurious Noise
–86
dB typ
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
Intermodulation Distortion (IMD)
Second Order Terms
–86
dB typ
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
Third Order Terms
–88
dB typ
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
Track/Hold Acquisition Time
2
s max
DC ACCURACY
Resolution
14
Bits
Minimum Resolution
14
Bits
No Missing Codes Are Guaranteed
Integral Nonlinearity
±2
LSB max
Differential Nonlinearity
±1
LSB max
Bipolar Zero Error
±20
LSB max
Positive Gain Error
5
±20
LSB max
Negative Gain Error
5
±20
LSB max
ANALOG INPUT
Input Voltage Range
±3
Volts
Input Current
±1
mA max
REFERENCE OUTPUT
6
RO ADC @ +25
°C
2.99/3.01
V min/ V max
RO ADC TC
±25
ppm/
°C typ
±40
±ppm/°C max
Reference Load Sensitivity
(
RO ADC vs. I)
–1.5
mV max
Reference Load Current Change (0–500
A),
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUTS
(
CONVST, CLK, CONTROL)
Input High Voltage, VINH
2.4
V min
VDD = 5 V ± 5%
Input Low Voltage, VINL
0.8
V max
VDD = 5 V ± 5%
Input Current, IIN
±10
A max
VIN = 0 V to VDD
Input Current
7 (CONTROL & CLK)
±10
A max
VIN = VSS to DGND
Input Capacitance, CIN
8
10
pF max
LOGIC OUTPUTS
DR,
RFS Outputs
Output Low Voltage, VOL
0.4
V max
ISINK = 1.6 mA, Pull-Up Resistor = 4.7 k
RCLK Output
Output Low Voltage, VOL
0.4
V max
ISINK = 2.6 mA, Pull-Up Resistor = 2 k
DR,
RFS, RCLK Outputs
Floating-State Leakage Current
±10
A max
Floating-State Output Capacitance
8
15
pF max
CONVERSION TIME
External Clock
10
s max
Internal Clock
10
s max
The Internal Clock Has a Nominal Value of 2.0 MHz
POWER REQUIREMENTS
For Both DAC and ADC
VDD
+5
V nom
±5% for Specified Performance
VSS
–5
V nom
±5% for Specified Performance
IDD
22
mA max
Cumulative Current from the Two VDD Pins
ISS
12
mA max
Cumulative Current from the Two VSS Pins
Total Power Dissipation
170
mW max
Typically 130 mW
NOTES
1Temperature ranges are as follows: J Version, 0
°C to +70°C; A Version, –40°C to +85°C.
2V
IN = ± 3 V.
3SNR calculation includes distortion and noise components.
4SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
5Measured with respect to internal reference.
6For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
7Tying the CONTROL input to V
DD places the device in a factory test mode where normal operation is not exhibited.
8Sample tested @ +25
°C to ensure compliance.
Specifications subject to change without notice.
REV. B
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