參數(shù)資料
型號(hào)： AD7866BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/24頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 2CHAN DUAL 20TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 24mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，單極
配用： EVAL-AD7866CBZ-ND - BOARD EVALUATION AD7866
REV. A
AD7866
–21–
etch technique is generally best for ground planes because it gives
the best shielding. Both AGND pins of the AD7866 should be
sunk in the AGND plane. Digital and analog ground planes
should be joined at only one place. If the AD7866 is in a system
where multiple devices require an AGND to DGND connec-
tion, the connection should still be made at one point only,
a star ground point that should be established as close as
possible to the AD7866.
Avoid running digital lines under the device since these will
couple noise onto the die. The analog ground plane should be
allowed to run under the AD7866 to avoid noise coupling.
The power supply lines to the AD7866 should use the largest
trace possible to provide low impedance paths and to reduce the
effects of glitches on the power supply line. Fast switching signals
like clocks should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never be run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique
is by far the best but is not always possible with a double-sided
board. For this technique, the component side of the board is
dedicated to ground planes while signals are placed on the
solder side.
Good decoupling is also important. All analog supplies should be
decoupled with 10
F tantalum in parallel with 0.1 F capacitors
to AGND. All digital supplies should have at least a 0.1
F disk
ceramic capacitor to DGND. VDRIVE should have a 0.1
F ceramic
capacitor to DGND. To achieve the best results from these
decoupling components, place them as close as possible to the
device, ideally right up against it. The 0.1
F capacitors should
be common ceramic or surface-mount types, which have low
Effective Series Resistance (ESR) and Effective Series Inductance
(ESI), and provide a low impedance path to ground at high
frequencies for handling transient currents due to internal logic
switching. Figure 27 shows the recommended supply decoupling
scheme. For information on the decoupling requirements of each
reference configuration, see the Reference Configuration
Options section.
AGND
DGND
AD7866
DVDD
AVDD
0.1 F10 F
AGND
0.1 F
10 F
VDRIVE
0.1 F
Figure 27. Recommended Supply Decoupling Scheme
Evaluating the AD7866 Performance
The recommended layout for the AD7866 is outlined in the
evaluation board for the AD7866. The evaluation board package
includes a fully assembled and tested evaluation board, documen-
tation, and software for controlling the board from the PC via the
eval-controller board. The eval-controller board can be used in
conjunction with the AD7866 evaluation board, as well as many
other Analog Devices evaluation boards ending in the CB desig-
nator, to demonstrate/evaluate the ac and dc performance of the
AD7866.
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7866.
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