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| 型號： | AD7864BSZ-1REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DUAL 4CHAN 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 520k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 120mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
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AD7864
Rev. D | Page 19 of 28
When reading the output data registers after a conversion
sequence, that is, when BUSY goes low, the register pointer is
incremented on the rising edge of the RD signal, as shown in
. However, when reading the conversion results during
the conversion sequence, the pointer is not incremented until a
valid conversion result is in the register to be addressed. In this
case, the pointer is incremented when the conversion has ended
and the result has been transferred to the output data register.
This happens immediately before
EOC goes low, therefore EOC
may be used to enable the register contents onto the data bus,
as described in the
subsection within the
section. The pointer is reset to point
to Register 1 on the rising edge of the
RD signal when the last
conversion result in the sequence is being read. In the example
shown, this means that the pointer is set to Register 1 when the
contents of Register 3 are read.
DB0 TO DB11
OUTPUT
DRIVERS
OE NO. 1
NOT VALID
(VIN3)
(VIN1)
(VIN4)
OE NO. 2
OE NO. 3
OE NO. 4
2-BIT
COUNTER
VDRIVE
OE
RD
CS
RESET
DE
CO
DE
OUTPUT DATA REGISTERS
*THE POINTER IS NOT INCREMENTED BY A RISING EDGE ON RD UNTIL
THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER
IS RESET WHEN THE LAST CONVERSION RESULT IS READ.
FRSTDATA
POINTER*
AD7864
0
13
41
-0
14
Figure 14. Output Data Registers
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