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| 型號： | AD7864BSZ-1REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DUAL 4CHAN 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 520k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 120mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
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AD7864
Rev. D | Page 18 of 28
STANDBY MODE OPERATION
The AD7864 has a standby mode whereby the device can be
placed in a low current consumption mode (5 μA typical). The
AD7864 is placed in standby by bringing the Logic Input STBY
low. The AD7864 can be powered up again for normal opera-
tion by bringing STBY logic high. The output data buffers remain
operational while the AD7864 is in standby. This means the user
can continue to access the conversion results while the AD7864
is in standby. This feature can be used to reduce the average power
consumption in a system using low throughput rates. To reduce
average power consumption, the AD7864 can be placed in standby
at the end of each conversion sequence, that is, when BUSY
goes low and is taken out of standby again prior to the start of
the next conversion sequence. The time it takes the AD7864 to
come out of standby is referred to as the wake-up time. The
wake-up time limits the maximum throughput rate at which the
AD7864 can be operated when powering down between conver-
sion sequences. The AD7864 wakes up in approximately 2 μs when
using an external reference. The wake-up time is also 2 μs when
the standby time is less than 1 ms while using the internal refer-
ence.
shows the wake-up time of the AD7864 for
standby times greater than 1 ms. Note that when the AD7864
is left in standby for periods of time greater than 1 ms, the part
requires more than 2 μs to wake up. For example, after initial
power-up using the internal reference, the AD7864 requires
6 ms to power up. The maximum throughput rate that can be
achieved when powering down between conversions is 1/(tBUSY +
2 μs) = 100 kSPS, approximately. When operating the AD7864 in a
standby mode between conversions, the power savings can be
significant. For example, with a throughput rate of 10 kSPS, the
AD7864 is powered down (IDD = 5 μA) for 90 μs out of every
100 μs (see
).
Therefore, the average power consumption drops to
125/10 mW or 12.5 mW approximately.
STANDBY TIME (Seconds)
1.0
0.9
0
10
0.0001
0.001
0.01
0.1
1
0.6
0.3
0.2
0.1
0.8
0.7
0.4
0.5
PO
W
ER
-U
P
T
IM
E
(
m
s)
+105°C
+25°C
–40°C
01
34
1-
0
12
Figure 12. Power-Up Time vs. Standby Time Using the On-Chip Reference
(Decoupled with 0.1 μF Capacitor)
ACCESSING THE OUTPUT DATA REGISTERS
There are four output data registers, one for each of the four
possible conversion results from a conversion sequence. The
result of the first conversion in a conversion sequence is placed
in Register 1, the second result is placed in Register 2, and so
forth. For example, if the conversion sequence VIN1, VIN3, and
the results of the conversion on VIN1, VIN3, and VIN4 are placed in
Register 1 to Register 3, respectively. The output data register
pointer is reset to point to Register 1 at the end of the first con-
version in the sequence, immediately prior to EOC going low.
At this point, the logic output, FRSTDATA, goes logic high to
indicate that the output data register pointer is addressing Reg-
ister 1. When CS and RD are both logic low, the contents of the
addressed register are enabled onto the data bus (DB0 to DB11).
CONVST
BUSY
STBY
100s
7s
tBUSY
IDD = 20A
tBUSY
2s
tWAKE-UP
01
34
1-
01
3
Figure 13. Power-Down Between Conversion Sequences
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