參數(shù)資料
型號(hào)： AD7856KRZ
廠商： Analog Devices Inc
文件頁數(shù)： 10/32頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 8CHAN 5V 24SOIC
標(biāo)準(zhǔn)包裝： 31
位數(shù)： 14
采樣率（每秒）： 285k
數(shù)據(jù)接口： 8051，QSPI?，串行，SPI? µP
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 89.25mW
電壓電源： 模擬和數(shù)字
工作溫度： 0°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)偽差分，單極
AD7856
–18–
REV. A
PERFORMANCE CURVES
The following performance curves apply to Mode 2 operation
only. If a conversion is initiated in software, then a slight degra-
dation in SNR can be expected when in Mode 2 operation. As
the sampling instant cannot be guaranteed internally, nonequi-
distant sampling will occur, resulting in a rise in the noise floor.
Initiating conversions in software is not recommended for Mode
1 operation.
Figure 18 shows a typical FFT plot for the AD7856 at 190 kHz
sample rate and 10 kHz input frequency.
FREQUENCY –kHz
–115
010
–95
–75
–55
–35
–15
20
30
40
50
60
70
80
90
4096 POINT FFT
FSAMPLE = 190.476 kHz
FIN = 10.091 kHz
SNR = 79.2dB
Figure 18. FFT Plot
Figure 19 shows the SNR vs. Frequency for 5 V supply and a
4.096 external reference (5 V reference is typically 1 dB better
performance).
INPUT FREQUENCY – kHz
79
75
0
166
20
50
120
140
78
77
76
S(N+D)
RATIO
–
dB
10
80
100
Figure 19. SNR vs. Frequency
Figure 20 shows the Power Supply Rejection Ratio versus Fre-
quency for the part. The Power Supply Rejection Ratio is de-
fined as the ratio of the power in ADC output at frequency f to
the power of a full-scale sine wave.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power of a
full-scale sine wave. Here a 100 mV peak-to-peak sine wave is
coupled onto the AVDD supply while the digital supply is left
unaltered.
INPUT FREQUENCY – kHz
–72
–74
–90
0.91
100
13.4
25.7
38.3
50.3
–76
–78
–80
–88
PSRR
–
dB
–82
–84
–86
63.5
74.8
87.4
AVDD = DVDD = 5.0V
100mV p-p SINEWAVE ON AVDD
REFIN = 4.098 EXT REFERENCE
Figure 20. PSRR vs. Frequency
POWER-DOWN OPTIONS
The AD7856 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate. The power management options are selected by
programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the
SLEEP pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. The AD7856 can be fully or partially
powered down. When fully powered down, all the on-chip cir-
cuitry is powered down and IDD is 1
A typ. If a partial power-
down is selected, then all the on-chip circuitry except the reference
is powered down and IDD is 400 A typ. The choice of full or par-
tial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is
discussed in the next section–Power-Up Times. However, a
partial power-down does allow the on-chip reference to be used
externally even though the rest of the AD7856 circuitry is pow-
ered down. It also allows the AD7856 to be powered up faster
after a long power-down period when using the on-chip refer-
ence (See Power-Up Times–Using On-Chip Reference).
When using the
SLEEP pin, the power management bits PMGT1
and PMGT0 should be set to zero (default status on power-up).
Bringing the
SLEEP pin logic high ensures normal operation,
and the part does not power down at any stage. This may be
necessary if the part is being used at high throughput rates when
it is not possible to power down between conversions. If the user
wishes to power down between conversions at lower throughput
rates (i.e. <100 kSPS for the AD7856) to achieve better power
performances, then the
SLEEP pin should be tied logic low.
If the power-down options are to be selected in software only,
then the
SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down Be-
tween Conversions can be selected.
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