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參數(shù)資料
| 型號(hào)： | AD7835AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 14-Bit DAC |
| 中文描述： | QUAD, PARALLEL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PQFP44 |
| 封裝： | MO-112AA-1, MQFP-44 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 404K |
| 代理商： | AD7835AS |
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AD7834/AD7835
REV. A
–5–
AD7834 PIN DESCRIPTION
Pin Mnemonic
Description
V
CC
V
SS
V
DD
DGND
AGND
V
REF
(+)
V
REF
(–)
V
OUT
1 . . . V
OUT
4
DSG
Logic Power Supply; +5 V
±
5%.
Negative Analog Power Supply; –15 V
±
5%.
Positive Analog Power Supply; +15 V
±
5%.
Digital Ground.
Analog Ground.
Positive Reference Input. The positive reference voltage is referred to AGND.
Negative Reference Input. The negative reference voltage is referred to AGND.
DAC Outputs.
Device Sense Ground Input. Used in conjunction with the
CLR
input for power-on protection of the DACs.
When
CLR
is low, the DAC outputs are forced to the potential on the DSG pin.
Serial Data Input.
Clock input for writing data to the device.
Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the device
with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-parallel input
register are transferred on the rising edge of this signal.
Package Address Inputs. These inputs are hardwired high (V
CC
) or low (DGND) to assign dedicated package
addresses in a multipackage environment.
Package Address Enable Input. When low, this input allows normal operation of the device. When it is high, the
device ignores the package address (but not the channel address) in the serial data stream and loads the serial
data into the input registers. This feature is useful in a multipackage application where it can be used to load the
same data into the same channel in each package.
Load DAC Input (level sensitive). This input signal in conjunction with the
FSYNC
input signal, determines
how the analog outputs are updated. If
LDAC
is maintained high while new data is being loaded into the
device’s input registers, no change occurs on the analog outputs. Subsequently, when
LDAC
is brought low, the
contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs.
Alternatively, if
LDAC
is kept low while new data is shifted into the device, then the addressed DAC latch (and
corresponding analog output) is updated immediately on the rising edge of
FSYNC
.
Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs are
switched to the externally set potential on the DSG pin. When
CLR
is brought high, the signal outputs remain at
the DSG potential until
LDAC
is brought low. When
LDAC
is brought low, the analog outputs are switched
back to reflect their individual DAC output levels. As long as
CLR
remains low, the
LDAC
signals are ignored
and the signal outputs remain switched to the potential on the DSG pin.
DIN
SCLK
FSYNC
PA0 . . . PA4
PAEN
LDAC
CLR
PIN CONFIGURATION
DIP AND SOIC
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
28
27
26
25
24
23
22
21
TOP VIEW
(Not to Scale)
NC = NO CONNECT
V
SS
DSG
NC
NC
NC
AGND
V
REF
(–)
V
REF
(+)
V
OUT
1
V
OUT
3
V
DD
NC
NC
V
OUT
2
V
OUT
4
DGND
V
CC
SCLK
LDAC
CLR
DIN
PA0
PA1
PA2
FSYNC
PA3
PA4
PAEN
AD7834
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