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參數(shù)資料
| 型號： | AD7835AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 14-Bit DAC |
| 中文描述： | QUAD, PARALLEL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PQFP44 |
| 封裝： | MO-112AA-1, MQFP-44 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 404K |
| 代理商： | AD7835AS |
AD7834/AD7835
REV. A
–13–
rial word length of the SPORT to 12 bits, with the following
conditions: Internal SCLK; Alternate framing mode; Active low
framing signal. Data can be transferred using the Autobuffering
feature of the ADSP-2101, sending two 12-bit words directly af-
ter each other. This ensures a continuous TFS pulse. Alterna-
tively, the first data word can be loaded to the serial port, the
subsequent interrupt that is generated can be trapped and then
the second data word can be sent immediately after the first.
Again this produces a continuous TFS pulse that frames the 24
data bits.
AD7834 to DSP56000/DSP56001 Interface
Figure 23 shows a serial interface between the AD7834 and the
DSP56000/DSP56001. The serial port is configured for a word
length of 24 bits, gated clock and with FSL0 and FSL1 control
bits each set to “0.” Normal Mode Synchronous operation is
selected which allows the use of SC0 and SC1 as outputs con-
trolling
CLR
and
LDAC
. The framing signal on SC2 has to be
inverted before being applied to FSYNC. SCK is internally
generated on the DSP56000/DSP56001 and is applied to SCLK
on the AD7834. Data from the DSP56000/DSP56001 is valid
on the falling edge of SCK.
CLR
LDAC
FSYNC
SCLK
DIN
SC1
SC2
SCK
STD
SC0
*
ADDITIONAL PINS OMITTED FOR CLARITY
AD7834
*
DSP56000/
DSP56001
*
Figure 23. AD7834 to DSP5600/DSP56001 Interface
AD7834 to TMS32020/TMS320C25
A serial interface between the AD7834 and the TMS32020/
TMS320C25 DSP processor is shown in Figure 24. The CLKX
and FSX signals for the TMS32020/TMS32025 should be gen-
erated using an external clock/timer circuit. The CLKX and
FSX pin should be configured as inputs. The TMS32020/
TMS320C25 should be set up for an 8-bit serial data length.
Data can then be written to the AD7834 by writing three bytes
to the serial port of the TMS32020/TMS320C25. In the con-
figuration shown in Figure 24 the
CLR
input on the AD7834 is
controlled by the XF output on the TMS32020/TMS320C25.
The clock/timer circuit controls the
LDAC
input on the
AD7834. Alternatively,
LDAC
could also be tied to ground to
allow automatic update of the DAC latches after each transfer.
CLR
LDAC
FSYNC
SCLK
DIN
XF
FSX
CLKX
DX
*
ADDITIONAL PINS OMITTED FOR CLARITY
AD7834
*
TMS32020/
TMS320C25
*
CLOCK/
TIMER
Figure 24. AD7834 to TMS32020/TMS320C25 Interface
Interfacing the AD7835—16-Bit Interface
The AD7835 can be interfaced to a variety of microcontrollers
or DSP processors, both 8-bit and 16-bit. Figure 25 shows the
AD7835 interfaced to a generic 16-bit microcontroller/DSP
processor.
BYSHF
is tied to V
CC
in this interface. The lower ad-
dress lines from the processor are connected to A0, A1 and A2
on the AD7835 as shown. The upper address lines are decoded
to provide a chip select signal for the AD7835. They are also
decoded (in conjunction with the lower address lines if need be)
to provide a
LDAC
signal. Alternatively,
LDAC
could be
driven by an external timing circuit or just tied low. The data
lines of the processor are connected to the data lines of the
AD7835. The selection of the DACs is as given in Table III.
*
ADDITIONAL PINS OMITTED FOR CLARITY
V
CC
ADDRESS
DECODE
AD7835
*
D13
D0
CS
LDAC
A2
A1
A0
WR
BYSHF
D13
D0
A2
A1
A0
R/
W
DATA
BUS
UPPER BITS OF
ADDRESS BUS
μCONTROLLER/
DSP
PROCESSOR
*
Figure 25. AD7835 16-Bit Interface
8-Bit Interface
Figure 26 shows an 8-bit interface between the AD7835 and a
generic 8-bit microcontroller/DSP processor. Pins D13 to D8
of the AD7835 are tied to DGND. Pins D7 to D0 of the pro-
cessor are connected to pins D7 to D0 of the AD7835.
BYSHF
is driven by the A0 line of the processor. This maps the DAC
upper bits and lower bits into adjacent bytes in the processors
address space. Table VI shows the truth table for addressing
the DACs in the AD7835. If, for example, the base address for
the DACs in the processor address space is decoded by the up-
per address bits to location HC000, then the first DAC’s upper
and lower bits are at locations HC000 and HC001 respectively.
*
ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS
DECODE
AD7835
*
D7
D0
CS
LDAC
A2
A1
A0
BYSHF
WR
D7
D0
A2
A1
A0
R/
W
DATA
BUS
UPPER BITS OF
ADDRESS BUS
μCONTROLLER/
DSP
PROCESSOR
*
D13
D8
A3
DGND
Figure 26. AD7835 8-Bit Interface
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