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參數(shù)資料
| 型號(hào)： | AD7834BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SC70 -40 to 125 |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PDSO28 |
| 封裝： | MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 404K |
| 代理商： | AD7834BR |
AD7834/AD7835
REV. A
–15–
V
OFFSET
voltage is adjusted until 0 V appears between the pin
driver output and DUT GND. This causes both V
REF
(+)A and
V
REF
(–)A to be offset with respect to AGND by an amount
equal to V
OFFSET
. However the output of the pin driver will vary
from –5 V to +5 V with respect to DUT GND as the DAC in-
put code varies from 000 . . . 000 to 111 . . . 111. The V
OFFSET
voltage is also applied to the DSG A pin. When a clear is per-
formed on the AD7835, the output of the pin driver will be 0 V
with respect to DUT GND.
*
ADDITIONAL PINS OMITTED FOR CLARITY
4
6
8
13
7
3
1
15
14
9
16
2
10 11 12
1μF
+15V –15V
0.1μF
AD588
4
6
8
13
10
11
12
7
3
1
15
14
16
2
1μF
+15V –15V
AD588
8
DUT
GND
TO TESTER
WINDOW
COMPARATOR
–15V
+15V
V
REF
(+)A
V
REF
(–)A
DSG A
V
REF
(+)B
V
REF
(–)B
AD7835
*
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
DSG B
AGND
DUT
GND
DUT
GND
V
DUT
V
OFFSET
PIN
DRIVER
Figure 29. ATE Application
The other AD588 is used to provide a reference voltage for
DACs 3 and 4. These provide the reference voltages for the
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to DUT GND. This causes V
REF
(+)B
and V
REF
(–)B to be referenced to DUT GND. As DAC 3 and
DAC 4 input codes vary from 000 . . . 000 to 111 . . . 111,
V
OUT
3 and V
OUT
4 vary from –5 V to +5 V with respect to DUT
GND. DUT GND is also connected to DSG B. When the
AD7835 is cleared, V
OUT
3 and V
OUT
4 are cleared to 0 V with
respect to DUT GND.
Care must be taken to ensure that the maximum and minimum
voltage specs for the AD7835 reference voltages are not broken
in the above configuration.
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7834/AD7835 is mounted should be designed such that the
analog and digital sections are separated and confined to certain
areas of the board. This facilitates the use of ground planes that
can be separated easily. A minimum etch technique is generally
best for ground planes as it gives the best shielding. Digital and
analog ground planes should only be joined at one place. If the
AD7834/AD7835 is the only device requiring an AGND to
DGND connection, then the ground planes should be con-
nected at the AGND and DGND pins of the AD7834/AD7835.
If the AD7834/AD7835 is in a system where multiple devices
require an AGND to DGND connection, the connection should
still be made at one point only, a star ground point which
should be established as close as possible to the AD7834/
AD7835.
Digital lines running under the device should be avoided as
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7834/AD7835 to avoid
noise coupling. The power supply lines of the AD7834/
AD7835 should use as large a trace as possible to provide low
impedance paths and reduce the effects of glitches on the power
supply line. Fast switching signals like clocks should be shielded
with digital ground to avoid radiating noise to other parts of the
board and should never be run near the analog inputs. Avoid
crossover of digital and analog signals. Traces on opposite sides
of the board should run at right angles to each other. This re-
duces the effects of feedthrough through the board. A
microstrip technique is by far the best but not always possible
with a double sided board. In this technique, the component
side of the board is dedicated to ground plane while signal traces
are placed on the solder side.
The AD7834/AD7835 should have ample supply bypassing lo-
cated as close to the package as possible, ideally right up against
the device. Figure 30 shows the recommended capacitor values
of 10
μ
F in parallel with 0.1
μ
F on each of the supplies. The
10
μ
F capacitors are the tantalum bead type. The 0.1
μ
F ca-
pacitor should have low Effective Series Resistance (ESR) and
Effective Series Inductance (ESI), such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
10μF
0.1μF
*
ADDITIONAL PINS OMITTED FOR CLARITY
10μF
0.1μF
10μF
0.1μF
AD7834/
AD7835
*
V
DD
V
CC
V
SS
AGND
DGND
Figure 30. Power Supply Decoupling
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