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參數(shù)資料
| 型號(hào)： | AD7834AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SOT-23 -40 to 125 |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, MS-011, DIP-28 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 404K |
| 代理商： | AD7834AN |
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AD7834/AD7835
REV. A
–7–
PIN CONFIGURATIONS
PQFP PLCC
9
10
11
12
13
7
8
16
17
14
15
2
1
44
3
4
5
6
42
41 40
43
35
36
37
38
39
33
34
31
32
29
30
18 19
20
21 22 23 24 25 26 27 28
D
PIN 1
TOP VIEW
(Not to Scale)
D
D
D
C
W
V
C
D
D
D
D
NC
DSGB
V
OUT
3
V
OUT
4
DB13
DB12
DB11
AD7835
NC
DSGA
V
OUT
1
V
OUT
2
NC
A2
A1
NC = NO CONNECT
A0
CLR
LDAC
BYSHF
DB10
DB9
DB8
DB7
N
V
R
(
N
V
S
V
D
A
N
V
R
(
V
R
(
N
V
R
(
12 13 14 15 16 17
C
W
18 19
20
21 22
D
3
4
5
6
7
1
2
10
11
8
9
40
39 38
41
42
43
44
36 35 34
37
29
30
31
32
27
28
25
26
23
24
33
PIN 1
TOP VIEW
(Not to Scale)
NC
DSGB
V
OUT
3
V
OUT
4
DB13
DB12
DB11
AD7835
D
V
C
D
D
D
D
D
D
NC
DSGA
V
OUT
1
V
OUT
2
NC
A2
A1
NC = NO CONNECT
A0
CLR
LDAC
BYSHF
DB10
DB9
DB8
DB7
N
V
R
(
V
R
(
N
V
S
V
D
A
N
N
V
R
(
V
R
(
TERMINOLOGY
Relative Accuracy
Relative Accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero error and full-scale error and is normally expressed in Least
Significant Bits or as a percentage of full-scale reading.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC Crosstalk
Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or other of the channel
outputs.
The four DAC outputs are buffered by op amps that share com-
mon V
DD
and V
SS
power supplies. If the dc load current changes
in one channel (due to an update), this can result in a further dc
change in one or other channel outputs. This effect is most ob-
vious at high load currents and reduces as the load currents are
reduced. With high impedance loads the effect is virtually
unmeasurable.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output when
the inputs change state. It is specified as the area of the glitch in
nV-secs. It is measured with the reference inputs connected to 0 V
and the digital inputs toggled between all 1s and all 0s.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DACs reference input which appears at the out-
put of the other DAC. It is expressed in dBs.
The AD7834 has no specification for Channel-to-channel isola-
tion because it has one reference for all DACs. Channel-to-
channel isolation is specified for the AD7835.
DAC-to-DAC Crosstalk
DAC-to-DAC Crosstalk is defined as the glitch impulse that ap-
pears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the V
OUT
pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s
loaded into the DAC latch, should be V
REF
(+) – 1 LSB. Full-
Scale Error does not include Zero-Scale Error.
Zero-Scale Error
Zero-Scale Error is the error in the DAC output voltage when
all 0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to V
REF
(–). Zero-
Scale Error is mainly due to offsets in the output amplifier.
Gain Error
Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7834AR | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SOT-23 -40 to 125 |
| AD7834BN | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SC70 -40 to 125 |
| AD7834BR | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SC70 -40 to 125 |
| AD7834SQ | LC2MOS Quad 14-Bit DAC |
| AD7835AP | LC2MOS Quad 14-Bit DAC |
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