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參數(shù)資料
| 型號： | AD7822BRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 1CH 2MSPS 20-SOIC |
| 標準包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 36mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
| 其它名稱： | AD7822BRZ-REEL7DKR |
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AD7822/AD7825/AD7829
Rev. C | Page 16 of 28
Mode 2 Operation (Automatic Power-Down)
When the AD7822/AD7825/AD7829 are operated in Mode 2
(see Figure 25), they automatically power down at the end of
a conversion. The CONVST signal is brought low to initiate
a conversion and is left logic low until after the EOC goes high,
that is, approximately 100 ns after the end of the conversion.
The state of the CONVST signal is sampled at this point (that is,
530 ns maximum after CONVST falling edge), and the AD7822/
AD7825/AD7829 power down as long as CONVST is low.
The ADC is powered up again on the rising edge of the
CONVST signal. Superior power performance can be achieved
in this mode of operation by powering up the AD7822/AD7825/
AD7829 only to carry out a conversion. The parallel interface of
the AD7822/AD7825/AD7829 remains fully operational while
the ADCs are powered down. A read may occur while the part
is powered down, and, therefore, it does not necessarily need to
be placed within the EOC pulse, as shown in Figure 25.
t2
t1
t3
VALID
DATA
CONVST
EOC
CS
RD
DB0 TO DB7
TRACK
HOLD
TRACK
HOLD
120ns
01
32
1-
0
25
Figure 24. Mode 1 Operation
CONVST
EOC
CS
RD
DB0 TO DB7
tPOWER-UP
t1
VALID
DATA
POWER
DOWN
HERE
01
32
1-
0
26
Figure 25. Mode 2 Operation
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| AD7822BRZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel Sampling ADCs |
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